;PALASM Design Description

;---------------------------------- Declaration Segment ------------
TITLE    512k SRAM extension for Atari XL
PATTERN  
REVISION 1.2
AUTHOR   Matthias Reichl
COMPANY  HiassofT
DATE     02/03/08

CHIP  ramdisk  PALCE22V10

;SIGNATURE HIAS

;---------------------------------- PIN Declarations ---------------

; connect to NPHI2_OUT
PIN 1	NPHI2_IN	COMBINATORIAL	; INPUT

; signals from CPU
PIN 2	A14	COMBINATORIAL	; INPUT
PIN 3	A15	COMBINATORIAL	; INPUT
PIN 4	HALT	COMBINATORIAL	; INPUT
PIN 5	RW	COMBINATORIAL	; INPUT
PIN 6	PHI2	COMBINATORIAL	; INPUT


; signals from PIA
PIN 7	PB4	COMBINATORIAL	; INPUT
PIN 8	PB5	COMBINATORIAL	; INPUT
PIN 9	PB7	COMBINATORIAL	; INPUT

; mode select input - active low!
PIN 10	/EN5	COMBINATORIAL	; INPUT
PIN 11	/EN7	COMBINATORIAL	; INPUT

;PIN 12	GND

; signal from CPU (used to shorten write cycles)
PIN 13	PHI0	COMBINATORIAL	; INPUT

; signal to MMU socket pin 16
PIN 14	/CASINH_OUT	COMBINATORIAL	; OUTPUT

; signal to MMU pin 6 
PIN 15	MAP	COMBINATORIAL	; OUTPUT

; signal from MMU pin 16
PIN 16	/CASINH_IN	COMBINATORIAL	; INPUT


; signals to RAM
PIN 17	/OE	COMBINATORIAL	; OUTPUT
PIN 18	/CE	COMBINATORIAL	; OUTPUT
PIN 19	/WE	COMBINATORIAL	; OUTPUT
PIN 20	RA17	COMBINATORIAL	; OUTPUT
PIN 21	RA15	COMBINATORIAL	; OUTPUT

; leave unconnected!
PIN 22	RHALT	REGISTERED	; OUTPUT

; connect to NPHI2_IN
PIN 23	NPHI2_OUT	COMBINATORIAL	; OUTPUT

;PIN 24		VCC

; ramdisk modes (set by EN5 and EN7, active low!)
; /EN7 = 1  /EN5 = 1  : RD off
; /EN7 = 1  /EN5 = 0  : 256k Rambo style RD
; /EN7 = 0  /EN5 = 1  : 256k CompyShop ramdisk, separate ANTIC access
; /EN7 = 0  /EN5 = 0  : 512k ramdisk

; separate cpu access in compy shop mode
; or cpu/antic access in other modes
STRING CPU_ACCESS '((EN7 * /EN5 * /PB4 * RHALT) + (EN5 * /PB4))'

; separate antic access only available in compy shop mode
STRING ANTIC_ACCESS '(EN7 * /EN5 * /PB5 * /RHALT)'


;----------------------------------- Boolean Equation Segment ------
EQUATIONS

; negate phi2 for HALT register

NPHI2_OUT = /PHI2

; create a register for HALT, clocked by the falling edge of phi2

RHALT := HALT
RHALT.CLKF = NPHI2_IN

; check for extended RAM access

; SRAM signal timing:
; - CASINH is set as soon as extended RAM access is detected
; - CE is set in the second half of cycle (PHI2 = high)
; - read access: OE set in second half of cycle, WE cleared
; - write access: WE set when both PHI0 and PHI2 are high
;   (slightly shortened cycle), OE cleared

IF /CASINH_IN * /A15 * A14 * (CPU_ACCESS + ANTIC_ACCESS) THEN
  BEGIN
    CE = PHI2
    CASINH_OUT = VCC
    IF RW THEN
      BEGIN
        OE = PHI2
        WE = GND
      END
    ELSE
      BEGIN
        OE = GND
        WE = PHI2 * PHI0
      END
  END
ELSE
  BEGIN
    CASINH_OUT = CASINH_IN
    CE = GND
    OE = GND
    WE = GND
  END

; disable selftest if EN7 and ramdisk enabled
IF EN7 * (/PB4 + (/PB5 * /EN5)) THEN
  BEGIN
    MAP = VCC
  END
ELSE
  BEGIN
    MAP = PB7
  END

; set RAM address line, depending on current mode settings
IF EN5 THEN
  BEGIN
    RA15 = PB5
  END
ELSE
  BEGIN
    RA15 = GND
  END

IF EN7 THEN
  BEGIN
    RA17 = PB7
  END
ELSE
  BEGIN
    RA17 = GND
  END

;----------------------------------- Simulation Segment ------------
SIMULATION

SETF PHI0 PHI2 /EN5 /EN7 PB4 PB5 PB7 /CASINH_IN
CHECK /CE /CASINH_OUT

; check halt register
SETF /HALT
CLOCKF NPHI2_IN
CHECK /RHALT
SETF HALT
CLOCKF NPHI2_IN
CHECK RHALT

; check PB5/PB7 address pass-through
SETF /EN5 /EN7 PB5 PB7
CHECK /RA15 /RA17

SETF EN5 /EN7 PB5 PB7
CHECK RA15 /RA17

SETF /EN5 EN7 PB5 PB7
CHECK /RA15 RA17

; check MAP pass-through
SETF /EN7 PB7
CHECK MAP
SETF /EN7 /PB7
CHECK /MAP
SETF /PB4 EN7 PB7
CHECK MAP
SETF /PB7
CHECK MAP

; check standard ram access
SETF /EN5 /EN7 PB4 PB5 PB7
SETF /A14 /A15
CHECK /CE /CASINH_OUT
SETF A14 /A15
CHECK /CE /CASINH_OUT
SETF /A14 A15
CHECK /CE /CASINH_OUT
SETF A14 A15
CHECK /CE /CASINH_OUT

; check 512k ramdisk access
SETF EN5 EN7 /PB4

SETF /A14 /A15
CHECK /CE /CASINH_OUT
SETF A14 /A15
CHECK CE CASINH_OUT
SETF /A14 A15
CHECK /CE /CASINH_OUT
SETF A14 A15
CHECK /CE /CASINH_OUT

; check 256k rambo mode
SETF EN5 /EN7 /PB4 PB5

SETF /A14 /A15
CHECK /CE /CASINH_OUT
SETF A14 /A15
CHECK CE CASINH_OUT
SETF /A14 A15
CHECK /CE /CASINH_OUT
SETF A14 A15
CHECK /CE /CASINH_OUT

; check 256k compy-shop mode
SETF /EN5 EN7 /PB4 /PB5 HALT
CLOCKF NPHI2_IN

SETF /A14 /A15
CHECK /CE /CASINH_OUT
SETF A14 /A15
CHECK CE CASINH_OUT
SETF /A14 A15
CHECK /CE /CASINH_OUT
SETF A14 A15
CHECK /CE /CASINH_OUT

; check CPU only access
SETF A14 /A15 /PB4 PB5 HALT
CLOCKF NPHI2_IN
CHECK CE CASINH_OUT
SETF PB4 /PB5
CHECK /CE /CASINH_OUT
SETF PB4 /PB5 /HALT
CLOCKF NPHI2_IN
CHECK CE CASINH_OUT
SETF /PB4 PB5
CHECK /CE /CASINH_OUT

; check CE, OE AND WE timing
SETF EN5 EN7 /PB4 PB5 PB7 A14 /A15 /PHI0 /PHI2 RW
CHECK /CE CASINH_OUT /OE /WE

; CE, OE depend on PHI2
SETF PHI2
CHECK CE CASINH_OUT OE /WE

; WE depends on PHI2 * PHI0
SETF /RW PHI0
CHECK CE CASINH_OUT /OE WE


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