Turbo-Freezer 2011 errata PLD board schematics: - The CPLD is a Xilinx XC95144XL-TQ100 (not a XC9572XL-TQ100) - IC1 is a 74HCT123 (not a 74LS123) - R2 should be changed to 5k6 (6k8 can result in marginal write timing) - Pin 1 of JP4 (the JTAG connector) should be connected to +3V3 (not VCC/5V) Memory board schematics: - SST39SF040 can be used instead of AM29F040 (this requires flasher 2.1 or newer) Memory board assembly: The A9 solder jumper on the component side must be connected by a blob of solder.