cpldfit:  version M.81d                             Xilinx Inc.
                                  Fitter Report
Design Name: TheCart                             Date: 10-27-2013,  1:13PM
Device Used: XC95144XL-10-TQ100
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
135/144 ( 94%) 585 /720  ( 81%) 374/432 ( 87%)   50 /144 ( 35%) 75 /81  ( 93%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          18/18*      48/54       84/90      10/11
FB2          15/18       47/54       86/90       8/10
FB3          17/18       47/54       68/90       9/10
FB4          18/18*      42/54       39/90      10/10*
FB5          15/18       48/54       74/90       9/10
FB6          18/18*      48/54       80/90       9/10
FB7          16/18       49/54       76/90      10/10*
FB8          18/18*      45/54       78/90      10/10*
             -----       -----       -----      -----    
            135/144     374/432     585/720     75/81 

* - Resource is exhausted

** Global Control Resources **

Signal 'phi2short' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   20          20    |  I/O              :    68      73
Output        :   38          38    |  GCK/IO           :     3       3
Bidirectional :   16          16    |  GTS/IO           :     3       4
GCK           :    1           1    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     75          75

** Power Data **

There are 0 macrocells in high performance mode (MCHP).
There are 135 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'TheCart.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'cctl' based upon the LOC
   constraint 'P27'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
INFO:Cpld - Inferring BUFG constraint for signal 'phi2' based upon the LOC
   constraint 'P22'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'phi2_IBUF' is
   ignored. Most likely the signal is gated and therefore cannot be used as a
   global control signal.
WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'cctl_IBUF' is
   ignored. Most likely the signal is gated and therefore cannot be used as a
   global control signal.
*************************  Summary of Mapped Logic  ************************

** 54 Outputs **

Signal                                                                          Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                                                            Pts   Inps          No.  Type    Use     Mode Rate State
data<0>                                                                         10    15    FB1_2   11   I/O     I/O     LOW  SLOW 
data<7>                                                                         5     11    FB1_3   12   I/O     I/O     LOW  SLOW 
data<6>                                                                         4     9     FB1_5   13   I/O     I/O     LOW  SLOW 
eeprom_cs                                                                       4     11    FB1_9   16   I/O     O       LOW  SLOW SET
eeprom_sck                                                                      4     11    FB1_12  18   I/O     O       LOW  SLOW RESET
eeprom_si                                                                       4     11    FB1_15  20   I/O     O       LOW  SLOW RESET
data<4>                                                                         7     12    FB2_5   1    GTS/I/O I/O     LOW  SLOW 
data<5>                                                                         7     12    FB2_11  6    I/O     I/O     LOW  SLOW 
data<2>                                                                         8     13    FB2_14  8    I/O     I/O     LOW  SLOW 
data<1>                                                                         8     13    FB2_15  9    I/O     I/O     LOW  SLOW 
data<3>                                                                         8     13    FB2_17  10   I/O     I/O     LOW  SLOW 
ram_rom_adr<26>                                                                 2     3     FB3_5   24   I/O     O       LOW  SLOW 
ram_rom_adr<0>                                                                  1     1     FB3_6   25   I/O     O       LOW  SLOW 
ram_rom_adr<17>                                                                 4     9     FB3_9   28   I/O     O       LOW  SLOW 
ram_rom_adr<25>                                                                 2     3     FB3_11  29   I/O     O       LOW  SLOW 
rom_reset                                                                       1     1     FB3_12  30   I/O     O       LOW  SLOW RESET
ram_rom_data<7>                                                                 2     2     FB3_14  32   I/O     I/O     LOW  SLOW 
ram_rom_data<6>                                                                 2     2     FB3_15  33   I/O     I/O     LOW  SLOW 
ram_rom_data<5>                                                                 2     2     FB5_2   35   I/O     I/O     LOW  SLOW 
ram_rom_data<4>                                                                 2     2     FB5_5   36   I/O     I/O     LOW  SLOW 
ram_rom_data<3>                                                                 2     2     FB5_6   37   I/O     I/O     LOW  SLOW 
ram_rom_data<2>                                                                 2     2     FB5_8   39   I/O     I/O     LOW  SLOW 
ram_rom_data<1>                                                                 2     2     FB5_9   40   I/O     I/O     LOW  SLOW 
ram_rom_data<0>                                                                 2     2     FB5_11  41   I/O     I/O     LOW  SLOW 
ram_rom_oe                                                                      1     2     FB5_12  42   I/O     O       LOW  SLOW 
ram_rom_adr<1>                                                                  1     1     FB5_14  43   I/O     O       LOW  SLOW 
rom_ce                                                                          8     12    FB5_17  49   I/O     O       LOW  SLOW 
ram_rom_adr<15>                                                                 6     9     FB6_2   74   I/O     O       LOW  SLOW 
ram_rom_adr<16>                                                                 4     8     FB6_5   76   I/O     O       LOW  SLOW 
ram_rom_adr<23>                                                                 2     3     FB6_6   77   I/O     O       LOW  SLOW 
ram_rom_adr<24>                                                                 2     3     FB6_8   78   I/O     O       LOW  SLOW 
rd5                                                                             9     11    FB6_9   79   I/O     O       LOW  SLOW 
rd4                                                                             6     9     FB6_12  81   I/O     O       LOW  SLOW 
ram_ce                                                                          6     12    FB6_15  85   I/O     O       LOW  SLOW 
ram_rom_we                                                                      1     2     FB7_2   50   I/O     O       LOW  SLOW 
ram_rom_adr<2>                                                                  1     1     FB7_5   52   I/O     O       LOW  SLOW 
ram_rom_adr<3>                                                                  1     1     FB7_6   53   I/O     O       LOW  SLOW 
ram_rom_adr<4>                                                                  1     1     FB7_8   54   I/O     O       LOW  SLOW 
ram_rom_adr<5>                                                                  1     1     FB7_9   55   I/O     O       LOW  SLOW 
ram_rom_adr<6>                                                                  1     1     FB7_11  56   I/O     O       LOW  SLOW 

Signal                                                                          Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                                                            Pts   Inps          No.  Type    Use     Mode Rate State
ram_rom_adr<7>                                                                  1     1     FB7_12  58   I/O     O       LOW  SLOW 
ram_rom_adr<8>                                                                  1     1     FB7_14  59   I/O     O       LOW  SLOW 
ram_rom_adr<18>                                                                 3     8     FB7_15  60   I/O     O       LOW  SLOW 
ram_rom_adr<19>                                                                 3     9     FB7_17  61   I/O     O       LOW  SLOW 
ram_rom_adr<22>                                                                 2     3     FB8_2   63   I/O     O       LOW  SLOW 
ram_rom_adr<21>                                                                 2     3     FB8_5   64   I/O     O       LOW  SLOW 
ram_rom_adr<20>                                                                 2     3     FB8_6   65   I/O     O       LOW  SLOW 
ram_rom_adr<9>                                                                  1     1     FB8_8   66   I/O     O       LOW  SLOW 
ram_rom_adr<10>                                                                 1     1     FB8_9   67   I/O     O       LOW  SLOW 
ram_rom_adr<11>                                                                 1     1     FB8_11  68   I/O     O       LOW  SLOW 
ram_rom_adr<12>                                                                 5     7     FB8_12  70   I/O     O       LOW  SLOW 
ram_rom_adr<13>                                                                 12    15    FB8_14  71   I/O     O       LOW  SLOW 
ram_rom_adr<14>                                                                 3     7     FB8_15  72   I/O     O       LOW  SLOW 
mod_en                                                                          6     11    FB8_17  73   I/O     O       LOW  SLOW SET

** 81 Buried Nodes **

Signal                                                                          Total Total Loc     Pwr  Reg Init
Name                                                                            Pts   Inps          Mode State
$OpTx$FX_DC$6                                                                   1     4     FB1_1   LOW  
use_cart_logic/cfg_bank2<20>                                                    3     7     FB1_4   LOW  RESET
use_cart_logic/cfg_bank2<15>                                                    3     7     FB1_6   LOW  RESET
use_cart_logic/cfg_bank2<14>                                                    3     7     FB1_7   LOW  RESET
use_cart_logic/cfg_bank2<13>                                                    3     7     FB1_8   LOW  RESET
use_cart_logic/cfg_mode<5>                                                      5     11    FB1_10  LOW  RESET
use_cart_logic/cfg_mode<4>                                                      5     11    FB1_11  LOW  RESET
use_cart_logic/cfg_write_enable2                                                6     11    FB1_13  LOW  RESET
use_cart_logic/cfg_source_ram                                                   6     11    FB1_14  LOW  RESET
use_cart_logic/cfg_enable2                                                      6     8     FB1_16  LOW  RESET
use_cart_logic/cfg_bank<23>                                                     6     11    FB1_17  LOW  RESET
use_cart_logic/cfg_bank<13>                                                     6     10    FB1_18  LOW  RESET
use_cart_logic/cfg_bank<25>                                                     6     11    FB2_1   LOW  RESET
use_cart_logic/cfg_bank<26>                                                     6     11    FB2_3   LOW  RESET
use_cart_logic/cfg_source_ram2                                                  6     11    FB2_4   LOW  RESET
use_cart_logic/cfg_bank2<24>                                                    5     12    FB2_6   LOW  RESET
use_cart_logic/cfg_bank2<25>                                                    5     12    FB2_7   LOW  RESET
use_cart_logic/cfg_bank2<26>                                                    5     12    FB2_8   LOW  RESET
use_cart_logic/cfg_mode<3>                                                      5     11    FB2_9   LOW  RESET
use_cart_logic/cfg_bank2<16>                                                    3     7     FB2_10  LOW  RESET
use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2                    1     4     FB2_12  LOW  
use_cart_logic/cfg_bank<24>                                                     6     11    FB2_18  LOW  RESET
$OpTx$FX_DC$22                                                                  1     3     FB3_1   LOW  
use_cart_logic/cfg_bank<20>                                                     11    15    FB3_2   LOW  RESET
use_cart_logic/N145/use_cart_logic/N145_D2                                      7     10    FB3_3   LOW  
use_cart_logic/oss_bank<1>                                                      6     12    FB3_4   LOW  RESET
$OpTx$FX_DC$107                                                                 5     11    FB3_7   LOW  
use_cart_logic/sic_axxx_enable                                                  3     6     FB3_8   LOW  SET
$OpTx$FX_DC$42                                                                  2     3     FB3_10  LOW  
$OpTx$FX_SC$112                                                                 2     4     FB3_13  LOW  
use_cart_logic/N230/use_cart_logic/N230_D2                                      2     5     FB3_16  LOW  
use_cart_logic/cfg_enable                                                       15    20    FB3_17  LOW  SET
use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2  1     8     FB4_1   LOW  
reset_n_sync1                                                                   1     1     FB4_2   LOW  RESET
reset_n_sync                                                                    1     1     FB4_3   LOW  RESET
$OpTx$FX_DC$7                                                                   1     2     FB4_4   LOW  
$OpTx$FX_DC$56                                                                  1     2     FB4_5   LOW  
$OpTx$FX_DC$36                                                                  1     2     FB4_6   LOW  
$OpTx$FX_DC$23                                                                  1     2     FB4_7   LOW  
$OpTx$FX_DC$137                                                                 1     2     FB4_8   LOW  

Signal                                                                          Total Total Loc     Pwr  Reg Init
Name                                                                            Pts   Inps          Mode State
data_or0000/data_or0000_D2                                                      2     7     FB4_9   LOW  
$OpTx$FX_DC$9                                                                   2     5     FB4_10  LOW  
$OpTx$FX_DC$43                                                                  2     5     FB4_11  LOW  
$OpTx$FX_DC$33                                                                  2     5     FB4_12  LOW  
use_cart_logic/sic_8xxx_enable                                                  3     6     FB4_13  LOW  RESET
use_cart_logic/cfg_bank2<19>                                                    3     7     FB4_14  LOW  RESET
use_cart_logic/cfg_bank2<18>                                                    3     7     FB4_15  LOW  RESET
use_cart_logic/cfg_bank2<17>                                                    3     7     FB4_16  LOW  RESET
data_1_IOBUFE/data_1_IOBUFE_TRST                                                3     7     FB4_17  LOW  
$OpTx$INV$3                                                                     8     10    FB4_18  LOW  
use_cart_logic/cfg_bank<14>                                                     15    27    FB5_1   LOW  RESET
use_cart_logic/cfg_bank<16>                                                     14    21    FB5_4   LOW  RESET
$OpTx$FX_DC$124                                                                 1     6     FB5_7   LOW  
use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2                    5     5     FB5_10  LOW  
use_cart_logic/cfg_bank<15>                                                     15    26    FB5_13  LOW  RESET
$OpTx$FX_DC$35                                                                  2     4     FB5_15  LOW  
$OpTx$BIN_OR$350                                                                13    23    FB6_1   LOW  
use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2        1     7     FB6_3   LOW  
$OpTx$FX_DC$19                                                                  1     6     FB6_4   LOW  
use_cart_logic/N26/use_cart_logic/N26_D2                                        3     5     FB6_7   LOW  
$OpTx$FX_DC$71                                                                  3     7     FB6_10  LOW  
$OpTx$FX_DC$70                                                                  3     13    FB6_11  LOW  
$OpTx$FX_DC$30                                                                  3     9     FB6_13  LOW  
$OpTx$FX_DC$84                                                                  4     13    FB6_14  LOW  
use_cart_logic/oss_bank<0>                                                      6     12    FB6_16  LOW  RESET
use_cart_logic/N19/use_cart_logic/N19_D2                                        7     8     FB6_17  LOW  
use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2        1     8     FB6_18  LOW  
$OpTx$INV$2                                                                     4     6     FB7_1   LOW  
$OpTx$FX_DC$158                                                                 3     6     FB7_3   LOW  
use_cart_logic/cfg_bank<18>                                                     11    20    FB7_4   LOW  RESET
use_cart_logic/cfg_bank<19>                                                     14    20    FB7_7   LOW  RESET
use_cart_logic/cfg_bank<17>                                                     15    22    FB7_13  LOW  RESET
$OpTx$BIN_STEP$349                                                              15    28    FB7_18  LOW  
use_cart_logic/cfg_mode<2>                                                      5     11    FB8_1   LOW  RESET
use_cart_logic/cfg_mode<1>                                                      5     11    FB8_3   LOW  RESET
use_cart_logic/cfg_bank2<23>                                                    5     12    FB8_4   LOW  RESET
use_cart_logic/cfg_bank2<22>                                                    5     12    FB8_7   LOW  RESET
use_cart_logic/cfg_bank2<21>                                                    5     12    FB8_10  LOW  RESET
use_cart_logic/cfg_mode<0>                                                      6     11    FB8_13  LOW  SET
use_cart_logic/cfg_bank<22>                                                     6     11    FB8_16  LOW  RESET

Signal                                                                          Total Total Loc     Pwr  Reg Init
Name                                                                            Pts   Inps          Mode State
use_cart_logic/cfg_bank<21>                                                     6     11    FB8_18  LOW  RESET

** 21 Inputs **

Signal                                                                          Loc     Pin  Pin     Pin     
Name                                                                                    No.  Type    Use     
adr<11>                                                                         FB1_6   14   I/O     I
adr<10>                                                                         FB1_8   15   I/O     I
eeprom_so                                                                       FB1_11  17   I/O     I
phi2                                                                            FB1_17  22   GCK/I/O I
rw                                                                              FB2_2   99   GSR/I/O I
s4                                                                              FB2_8   3    GTS/I/O I
s5                                                                              FB2_9   4    GTS/I/O I
phi2short                                                                       FB3_2   23   GCK/I/O GCK/I
cctl                                                                            FB3_8   27   GCK/I/O I
adr<4>                                                                          FB4_2   87   I/O     I
adr<2>                                                                          FB4_5   89   I/O     I
adr<5>                                                                          FB4_6   90   I/O     I
adr<1>                                                                          FB4_8   91   I/O     I
adr<6>                                                                          FB4_9   92   I/O     I
adr<0>                                                                          FB4_11  93   I/O     I
adr<7>                                                                          FB4_12  94   I/O     I
adr<8>                                                                          FB4_14  95   I/O     I
adr<9>                                                                          FB4_15  96   I/O     I
adr<12>                                                                         FB4_17  97   I/O     I
reset_n                                                                         FB6_14  82   I/O     I
adr<3>                                                                          FB6_17  86   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               48/6
Number of signals used by logic mapping into function block:  48
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
$OpTx$FX_DC$6         1       0   \/4   0     FB1_1         (b)     (b)
data<0>              10       5<-   0   0     FB1_2   11    I/O     I/O
data<7>               5       1<- /\1   0     FB1_3   12    I/O     I/O
use_cart_logic/cfg_bank2<20>
                      3       0   /\1   1     FB1_4         (b)     (b)
data<6>               4       0     0   1     FB1_5   13    I/O     I/O
use_cart_logic/cfg_bank2<15>
                      3       0     0   2     FB1_6   14    I/O     I
use_cart_logic/cfg_bank2<14>
                      3       0     0   2     FB1_7         (b)     (b)
use_cart_logic/cfg_bank2<13>
                      3       0   \/2   0     FB1_8   15    I/O     I
eeprom_cs             4       2<- \/3   0     FB1_9   16    I/O     O
use_cart_logic/cfg_mode<5>
                      5       3<- \/3   0     FB1_10        (b)     (b)
use_cart_logic/cfg_mode<4>
                      5       3<- \/3   0     FB1_11  17    I/O     I
eeprom_sck            4       3<- \/4   0     FB1_12  18    I/O     O
use_cart_logic/cfg_write_enable2
                      6       4<- \/3   0     FB1_13        (b)     (b)
use_cart_logic/cfg_source_ram
                      6       3<- \/2   0     FB1_14  19    I/O     (b)
eeprom_si             4       2<- \/3   0     FB1_15  20    I/O     O
use_cart_logic/cfg_enable2
                      6       3<- \/2   0     FB1_16        (b)     (b)
use_cart_logic/cfg_bank<23>
                      6       2<- \/1   0     FB1_17  22    GCK/I/O I
use_cart_logic/cfg_bank<13>
                      6       1<-   0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$BIN_STEP$349                17: eeprom_si                                   33: use_cart_logic/cfg_bank2<19> 
  2: $OpTx$FX_DC$23                    18: eeprom_so                                   34: use_cart_logic/cfg_bank2<20> 
  3: $OpTx$FX_DC$33                    19: mod_en                                      35: use_cart_logic/cfg_bank2<21> 
  4: $OpTx$FX_DC$6                     20: data<0>.PIN                                 36: use_cart_logic/cfg_bank<13> 
  5: ram_rom_data<0>.PIN               21: data<1>.PIN                                 37: use_cart_logic/cfg_bank<19> 
  6: ram_rom_data<7>.PIN               22: data<2>.PIN                                 38: use_cart_logic/cfg_bank<20> 
  7: ram_rom_data<6>.PIN               23: data<4>.PIN                                 39: use_cart_logic/cfg_bank<21> 
  8: adr<0>                            24: data<5>.PIN                                 40: use_cart_logic/cfg_bank<23> 
  9: adr<1>                            25: data<7>.PIN                                 41: use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 
 10: adr<2>                            26: reset_n                                     42: use_cart_logic/cfg_enable 
 11: adr<3>                            27: reset_n_sync                                43: use_cart_logic/cfg_enable2 
 12: cctl                              28: rw                                          44: use_cart_logic/cfg_mode<0> 
 13: data_1_IOBUFE/data_1_IOBUFE_TRST  29: use_cart_logic/N230/use_cart_logic/N230_D2  45: use_cart_logic/cfg_mode<4> 
 14: data_or0000/data_or0000_D2        30: use_cart_logic/cfg_bank2<13>                46: use_cart_logic/cfg_mode<5> 
 15: eeprom_cs                         31: use_cart_logic/cfg_bank2<14>                47: use_cart_logic/cfg_source_ram 
 16: eeprom_sck                        32: use_cart_logic/cfg_bank2<15>                48: use_cart_logic/cfg_write_enable2 

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
$OpTx$FX_DC$6        ..........XX...............XX..................... 4
data<0>              ....X..XXX..XX....X..........X....XX..X.XXXX...... 15
data<7>              .....X.XXXX.XX...X...............X...X..X......... 11
use_cart_logic/cfg_bank2<20> 
                     ...X...XXX..............X.X......X................ 7
data<6>              ......XXXX..XX..................X...X...X......... 9
use_cart_logic/cfg_bank2<15> 
                     ...X...XXX...........X....X....X.................. 7
use_cart_logic/cfg_bank2<14> 
                     ...X...XXX..........X.....X...X................... 7
use_cart_logic/cfg_bank2<13> 
                     ...X...XXX.........X......X..X.................... 7
eeprom_cs            .......XXXXX..X.....X....X.XX...........X......... 11
use_cart_logic/cfg_mode<5> 
                     ...X...XXXXX.X.........X..X.X................X.... 11
use_cart_logic/cfg_mode<4> 
                     ...X...XXXXX.X........X...X.X...............X..... 11
eeprom_sck           .......XXXXX...X...X.....X.XX...........X......... 11
use_cart_logic/cfg_write_enable2 
                     ...X...XXXXX.X.......X....X.X..................X.. 11
use_cart_logic/cfg_source_ram 
                     ...X...XXXXX.X......X.....X.X.................X... 11
eeprom_si            .......XXXXX....X.......XX.XX...........X......... 11
use_cart_logic/cfg_enable2 
                     ...X...XXX.........X......X.............X.X....... 8
use_cart_logic/cfg_bank<23> 
                     ...X...XXXXX.X.......X....X.X..........X.......... 11
use_cart_logic/cfg_bank<13> 
                     XXX........X..............X.X......X....X...XX.... 10
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               47/7
Number of signals used by logic mapping into function block:  47
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
use_cart_logic/cfg_bank<25>
                      6       5<- /\4   0     FB2_1         (b)     (b)
(unused)              0       0   /\5   0     FB2_2   99    GSR/I/O I
use_cart_logic/cfg_bank<26>
                      6       1<-   0   0     FB2_3         (b)     (b)
use_cart_logic/cfg_source_ram2
                      6       2<- /\1   0     FB2_4         (b)     (b)
data<4>               7       4<- /\2   0     FB2_5   1     GTS/I/O I/O
use_cart_logic/cfg_bank2<24>
                      5       4<- /\4   0     FB2_6   2     GTS/I/O (b)
use_cart_logic/cfg_bank2<25>
                      5       4<- /\4   0     FB2_7         (b)     (b)
use_cart_logic/cfg_bank2<26>
                      5       4<- /\4   0     FB2_8   3     GTS/I/O I
use_cart_logic/cfg_mode<3>
                      5       4<- /\4   0     FB2_9   4     GTS/I/O I
use_cart_logic/cfg_bank2<16>
                      3       2<- /\4   0     FB2_10        (b)     (b)
data<5>               7       4<- /\2   0     FB2_11  6     I/O     I/O
use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2
                      1       0   /\4   0     FB2_12  7     I/O     (b)
(unused)              0       0   \/3   2     FB2_13        (b)     (b)
data<2>               8       3<-   0   0     FB2_14  8     I/O     I/O
data<1>               8       3<-   0   0     FB2_15  9     I/O     I/O
(unused)              0       0   /\3   2     FB2_16        (b)     (b)
data<3>               8       3<-   0   0     FB2_17  10    I/O     I/O
use_cart_logic/cfg_bank<24>
                      6       4<- /\3   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$6                     17: reset_n_sync                                33: use_cart_logic/cfg_bank<18> 
  2: ram_rom_data<5>.PIN               18: use_cart_logic/N230/use_cart_logic/N230_D2  34: use_cart_logic/cfg_bank<22> 
  3: ram_rom_data<4>.PIN               19: use_cart_logic/cfg_bank2<14>                35: use_cart_logic/cfg_bank<23> 
  4: ram_rom_data<3>.PIN               20: use_cart_logic/cfg_bank2<15>                36: use_cart_logic/cfg_bank<24> 
  5: ram_rom_data<2>.PIN               21: use_cart_logic/cfg_bank2<16>                37: use_cart_logic/cfg_bank<25> 
  6: ram_rom_data<1>.PIN               22: use_cart_logic/cfg_bank2<17>                38: use_cart_logic/cfg_bank<26> 
  7: adr<0>                            23: use_cart_logic/cfg_bank2<18>                39: use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 
  8: adr<1>                            24: use_cart_logic/cfg_bank2<22>                40: use_cart_logic/cfg_mode<1> 
  9: adr<2>                            25: use_cart_logic/cfg_bank2<23>                41: use_cart_logic/cfg_mode<2> 
 10: adr<3>                            26: use_cart_logic/cfg_bank2<24>                42: use_cart_logic/cfg_mode<3> 
 11: cctl                              27: use_cart_logic/cfg_bank2<25>                43: use_cart_logic/cfg_mode<4> 
 12: data_1_IOBUFE/data_1_IOBUFE_TRST  28: use_cart_logic/cfg_bank2<26>                44: use_cart_logic/cfg_mode<5> 
 13: data_or0000/data_or0000_D2        29: use_cart_logic/cfg_bank<14>                 45: use_cart_logic/cfg_source_ram 
 14: data<3>.PIN                       30: use_cart_logic/cfg_bank<15>                 46: use_cart_logic/cfg_source_ram2 
 15: data<4>.PIN                       31: use_cart_logic/cfg_bank<16>                 47: use_cart_logic/cfg_write_enable2 
 16: data<5>.PIN                       32: use_cart_logic/cfg_bank<17>                

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
use_cart_logic/cfg_bank<25> 
                     X.....XXXXX.X.X.XX..................X............. 11
use_cart_logic/cfg_bank<26> 
                     X.....XXXXX.X..XXX...................X............ 11
use_cart_logic/cfg_source_ram2 
                     X.....XXXXX.XX..XX...........................X.... 11
data<4>              ..X...XXX..XX........X....X....X....X.X...X....... 12
use_cart_logic/cfg_bank2<24> 
                     X.....XXXXX.XX..XX.......X............X........... 12
use_cart_logic/cfg_bank2<25> 
                     X.....XXXXX.X.X.XX........X...........X........... 12
use_cart_logic/cfg_bank2<26> 
                     X.....XXXXX.X..XXX.........X..........X........... 12
use_cart_logic/cfg_mode<3> 
                     X.....XXXXX.XX..XX.......................X........ 11
use_cart_logic/cfg_bank2<16> 
                     X.....XXX....X..X...X............................. 7
data<5>              .X....XXX..XX.........X....X....X....XX....X...... 12
use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2 
                     .................X.......................XXX...... 4
data<2>              ....X.XXX..XX......X....X....X....X...X.X.....X... 13
data<1>              .....XXXX..XX.....X....X....X....X....XX....X..... 13
data<3>              ...X..XXX..XX.......X....X....X....X..X..X...X.... 13
use_cart_logic/cfg_bank<24> 
                     X.....XXXXX.XX..XX.................X.............. 11
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               47/7
Number of signals used by logic mapping into function block:  47
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
$OpTx$FX_DC$22        1       0   \/4   0     FB3_1         (b)     (b)
use_cart_logic/cfg_bank<20>
                     11       6<-   0   0     FB3_2   23    GCK/I/O GCK/I
use_cart_logic/N145/use_cart_logic/N145_D2
                      7       4<- /\2   0     FB3_3         (b)     (b)
use_cart_logic/oss_bank<1>
                      6       5<- /\4   0     FB3_4         (b)     (b)
ram_rom_adr<26>       2       2<- /\5   0     FB3_5   24    I/O     O
ram_rom_adr<0>        1       0   /\2   2     FB3_6   25    I/O     O
$OpTx$FX_DC$107       5       0     0   0     FB3_7         (b)     (b)
use_cart_logic/sic_axxx_enable
                      3       0     0   2     FB3_8   27    GCK/I/O I
ram_rom_adr<17>       4       0     0   1     FB3_9   28    I/O     O
$OpTx$FX_DC$42        2       0     0   3     FB3_10        (b)     (b)
ram_rom_adr<25>       2       0     0   3     FB3_11  29    I/O     O
rom_reset             1       0     0   4     FB3_12  30    I/O     O
$OpTx$FX_SC$112       2       0     0   3     FB3_13        (b)     (b)
ram_rom_data<7>       2       0     0   3     FB3_14  32    I/O     I/O
ram_rom_data<6>       2       0   \/2   1     FB3_15  33    I/O     I/O
use_cart_logic/N230/use_cart_logic/N230_D2
                      2       2<- \/5   0     FB3_16        (b)     (b)
use_cart_logic/cfg_enable
                     15      10<-   0   0     FB3_17  34    I/O     (b)
(unused)              0       0   /\5   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$124   17: adr<7>                                                        33: use_cart_logic/cfg_bank<20> 
  2: $OpTx$FX_DC$137   18: cctl                                                          34: use_cart_logic/cfg_bank<25> 
  3: $OpTx$FX_DC$158   19: data<6>.PIN                                                   35: use_cart_logic/cfg_bank<26> 
  4: $OpTx$FX_DC$19    20: data<7>.PIN                                                   36: use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2 
  5: $OpTx$FX_DC$22    21: reset_n_sync                                                  37: use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 
  6: $OpTx$FX_DC$36    22: rw                                                            38: use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2 
  7: $OpTx$FX_DC$42    23: s5                                                            39: use_cart_logic/cfg_enable 
  8: $OpTx$FX_DC$56    24: use_cart_logic/N145/use_cart_logic/N145_D2                    40: use_cart_logic/cfg_mode<0> 
  9: $OpTx$FX_DC$7     25: use_cart_logic/N230/use_cart_logic/N230_D2                    41: use_cart_logic/cfg_mode<1> 
 10: $OpTx$FX_SC$112   26: use_cart_logic/N26/use_cart_logic/N26_D2                      42: use_cart_logic/cfg_mode<2> 
 11: $OpTx$INV$2       27: use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2  43: use_cart_logic/cfg_mode<3> 
 12: $OpTx$INV$3       28: use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2  44: use_cart_logic/cfg_mode<4> 
 13: adr<0>            29: use_cart_logic/cfg_bank2<17>                                  45: use_cart_logic/cfg_mode<5> 
 14: adr<4>            30: use_cart_logic/cfg_bank2<25>                                  46: use_cart_logic/oss_bank<1> 
 15: adr<5>            31: use_cart_logic/cfg_bank2<26>                                  47: use_cart_logic/sic_axxx_enable 
 16: adr<6>            32: use_cart_logic/cfg_bank<17>                                  

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
$OpTx$FX_DC$22       .............XXX.................................. 3
use_cart_logic/cfg_bank<20> 
                     X....X...X.....X.XXXXX...X......X...X..X...XX..... 15
use_cart_logic/N145/use_cart_logic/N145_D2 
                     ........X.X..XXXX........X.X.............XX....... 10
use_cart_logic/oss_bank<1> 
                     ....XX......X...X...X...XX.............X.XXX.X.... 12
ram_rom_adr<26>      ...X..........................X...X............... 3
ram_rom_adr<0>       ............X..................................... 1
$OpTx$FX_DC$107      .....X..............XX.XX.X........XXX.....XX..... 11
use_cart_logic/sic_axxx_enable 
                     .................XX.XX...............X........X... 6
ram_rom_adr<17>      ...X..................X.....X..X.......XXX.XX..... 9
$OpTx$FX_DC$42       ...........X.........X................X........... 3
ram_rom_adr<25>      ...X.........................X...X................ 3
rom_reset            ....................X............................. 1
$OpTx$FX_SC$112      .....X...........X..XX............................ 4
ram_rom_data<7>      ...................X.X............................ 2
ram_rom_data<6>      ..................X..X............................ 2
use_cart_logic/N230/use_cart_logic/N230_D2 
                     .............XXXXX................................ 5
use_cart_logic/cfg_enable 
                     .XX..XXX..XX.....X.XXX.XX..........X..X.XXXXX..... 20
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               42/12
Number of signals used by logic mapping into function block:  42
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2
                      1       0   /\2   2     FB4_1         (b)     (b)
reset_n_sync1         1       0     0   4     FB4_2   87    I/O     I
reset_n_sync          1       0     0   4     FB4_3         (b)     (b)
$OpTx$FX_DC$7         1       0     0   4     FB4_4         (b)     (b)
$OpTx$FX_DC$56        1       0     0   4     FB4_5   89    I/O     I
$OpTx$FX_DC$36        1       0     0   4     FB4_6   90    I/O     I
$OpTx$FX_DC$23        1       0     0   4     FB4_7         (b)     (b)
$OpTx$FX_DC$137       1       0     0   4     FB4_8   91    I/O     I
data_or0000/data_or0000_D2
                      2       0     0   3     FB4_9   92    I/O     I
$OpTx$FX_DC$9         2       0     0   3     FB4_10        (b)     (b)
$OpTx$FX_DC$43        2       0     0   3     FB4_11  93    I/O     I
$OpTx$FX_DC$33        2       0     0   3     FB4_12  94    I/O     I
use_cart_logic/sic_8xxx_enable
                      3       0     0   2     FB4_13        (b)     (b)
use_cart_logic/cfg_bank2<19>
                      3       0     0   2     FB4_14  95    I/O     I
use_cart_logic/cfg_bank2<18>
                      3       0     0   2     FB4_15  96    I/O     I
use_cart_logic/cfg_bank2<17>
                      3       0     0   2     FB4_16        (b)     (b)
data_1_IOBUFE/data_1_IOBUFE_TRST
                      3       0   \/1   1     FB4_17  97    I/O     I
$OpTx$INV$3           8       3<-   0   0     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$36              15: data<4>.PIN                                 29: use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2 
  2: $OpTx$FX_DC$6               16: data<5>.PIN                                 30: use_cart_logic/cfg_bank2<17> 
  3: $OpTx$FX_DC$9               17: data<6>.PIN                                 31: use_cart_logic/cfg_bank2<18> 
  4: adr<0>                      18: rd4                                         32: use_cart_logic/cfg_bank2<19> 
  5: adr<1>                      19: rd5                                         33: use_cart_logic/cfg_bank<13> 
  6: adr<2>                      20: reset_n                                     34: use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 
  7: adr<3>                      21: reset_n_sync                                35: use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2 
  8: adr<4>                      22: reset_n_sync1                               36: use_cart_logic/cfg_enable 
  9: adr<5>                      23: rw                                          37: use_cart_logic/cfg_mode<0> 
 10: adr<6>                      24: s4                                          38: use_cart_logic/cfg_mode<1> 
 11: adr<7>                      25: s5                                          39: use_cart_logic/cfg_mode<2> 
 12: cctl                        26: use_cart_logic/N19/use_cart_logic/N19_D2    40: use_cart_logic/cfg_mode<3> 
 13: data_or0000/data_or0000_D2  27: use_cart_logic/N230/use_cart_logic/N230_D2  41: use_cart_logic/cfg_mode<4> 
 14: data<0>.PIN                 28: use_cart_logic/N26/use_cart_logic/N26_D2    42: use_cart_logic/sic_8xxx_enable 

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 
                     ...XXXXXXXX....................................... 8
reset_n_sync1        ...................X.............................. 1
reset_n_sync         .....................X............................ 1
$OpTx$FX_DC$7        ....................................X.X........... 2
$OpTx$FX_DC$56       .........XX....................................... 2
$OpTx$FX_DC$36       ............................X...........X......... 2
$OpTx$FX_DC$23       .....................................XX........... 2
$OpTx$FX_DC$137      ......X................................X.......... 2
data_or0000/data_or0000_D2 
                     ...XXXX....X..........X...X....................... 7
$OpTx$FX_DC$9        ...........X.X........X.........XX................ 5
$OpTx$FX_DC$43       ..X.................X......X....XX................ 5
$OpTx$FX_DC$33       X.X.................X...........XX................ 5
use_cart_logic/sic_8xxx_enable 
                     ...........X...X....X.X...........X......X........ 6
use_cart_logic/cfg_bank2<19> 
                     .X.XXX..........X...X..........X.................. 7
use_cart_logic/cfg_bank2<18> 
                     .X.XXX.........X....X.........X................... 7
use_cart_logic/cfg_bank2<17> 
                     .X.XXX........X.....X........X.................... 7
data_1_IOBUFE/data_1_IOBUFE_TRST 
                     ............X....XX...XXXX........................ 7
$OpTx$INV$3          ...XXXXXXXX..X.....................X.............. 10
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               48/6
Number of signals used by logic mapping into function block:  48
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
use_cart_logic/cfg_bank<14>
                     15      10<-   0   0     FB5_1         (b)     (b)
ram_rom_data<5>       2       0   /\3   0     FB5_2   35    I/O     I/O
(unused)              0       0   \/5   0     FB5_3         (b)     (b)
use_cart_logic/cfg_bank<16>
                     14       9<-   0   0     FB5_4         (b)     (b)
ram_rom_data<4>       2       1<- /\4   0     FB5_5   36    I/O     I/O
ram_rom_data<3>       2       0   /\1   2     FB5_6   37    I/O     I/O
$OpTx$FX_DC$124       1       0     0   4     FB5_7         (b)     (b)
ram_rom_data<2>       2       0     0   3     FB5_8   39    I/O     I/O
ram_rom_data<1>       2       0     0   3     FB5_9   40    I/O     I/O
use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2
                      5       0     0   0     FB5_10        (b)     (b)
ram_rom_data<0>       2       0   \/1   2     FB5_11  41    I/O     I/O
ram_rom_oe            1       1<- \/5   0     FB5_12  42    I/O     O
use_cart_logic/cfg_bank<15>
                     15      10<-   0   0     FB5_13        (b)     (b)
ram_rom_adr<1>        1       1<- /\5   0     FB5_14  43    I/O     O
$OpTx$FX_DC$35        2       0   /\1   2     FB5_15  46    I/O     (b)
(unused)              0       0   \/5   0     FB5_16        (b)     (b)
rom_ce                8       5<- \/2   0     FB5_17  49    I/O     O
(unused)              0       0   \/5   0     FB5_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$BIN_OR$350  17: phi2                                        33: use_cart_logic/N26/use_cart_logic/N26_D2 
  2: $OpTx$FX_DC$107   18: data<0>.PIN                                 34: use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2 
  3: $OpTx$FX_DC$23    19: data<1>.PIN                                 35: use_cart_logic/cfg_bank<14> 
  4: $OpTx$FX_DC$30    20: data<2>.PIN                                 36: use_cart_logic/cfg_bank<15> 
  5: $OpTx$FX_DC$35    21: data<3>.PIN                                 37: use_cart_logic/cfg_bank<16> 
  6: $OpTx$FX_DC$36    22: data<4>.PIN                                 38: use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 
  7: $OpTx$FX_DC$7     23: data<5>.PIN                                 39: use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2 
  8: $OpTx$FX_DC$70    24: rd4                                         40: use_cart_logic/cfg_mode<0> 
  9: $OpTx$FX_SC$112   25: rd5                                         41: use_cart_logic/cfg_mode<1> 
 10: $OpTx$INV$2       26: reset_n_sync                                42: use_cart_logic/cfg_mode<2> 
 11: adr<0>            27: rw                                          43: use_cart_logic/cfg_mode<3> 
 12: adr<1>            28: s4                                          44: use_cart_logic/cfg_mode<4> 
 13: adr<2>            29: s5                                          45: use_cart_logic/cfg_mode<5> 
 14: adr<7>            30: use_cart_logic/N145/use_cart_logic/N145_D2  46: use_cart_logic/cfg_source_ram 
 15: cctl              31: use_cart_logic/N19/use_cart_logic/N19_D2    47: use_cart_logic/cfg_source_ram2 
 16: mod_en            32: use_cart_logic/N230/use_cart_logic/N230_D2  48: use_cart_logic/cfg_write_enable2 

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
use_cart_logic/cfg_bank<14> 
                     .XXX.XX.XXXX..X..XX......XX..X.XXXX..XXXXXXXX..... 27
ram_rom_data<5>      ......................X...X....................... 2
use_cart_logic/cfg_bank<16> 
                     X...X.XXX....XX....XX....XX....XXX..XX..XXXXX..... 21
ram_rom_data<4>      .....................X....X....................... 2
ram_rom_data<3>      ....................X.....X....................... 2
$OpTx$FX_DC$124      ..X..............................X.....X..XXX..... 6
ram_rom_data<2>      ...................X......X....................... 2
ram_rom_data<1>      ..................X.......X....................... 2
use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2 
                     .......................................XXXX.X..... 5
ram_rom_data<0>      .................X........X....................... 2
ram_rom_oe           ................X.........X....................... 2
use_cart_logic/cfg_bank<15> 
                     .X.X.XXXXX.XX.X...XX.....XX..X.XX..X.XXXXXXXX..... 26
ram_rom_adr<1>       ...........X...................................... 1
$OpTx$FX_DC$35       .....X...................XX..........X............ 4
rom_ce               ...............X.......XX.XXX.X..........X..XXXX.. 12
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               48/6
Number of signals used by logic mapping into function block:  48
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
$OpTx$BIN_OR$350     13       8<-   0   0     FB6_1         (b)     (b)
ram_rom_adr<15>       6       5<- /\4   0     FB6_2   74    I/O     O
use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2
                      1       1<- /\5   0     FB6_3         (b)     (b)
$OpTx$FX_DC$19        1       0   /\1   3     FB6_4         (b)     (b)
ram_rom_adr<16>       4       0     0   1     FB6_5   76    I/O     O
ram_rom_adr<23>       2       0     0   3     FB6_6   77    I/O     O
use_cart_logic/N26/use_cart_logic/N26_D2
                      3       0   \/1   1     FB6_7         (b)     (b)
ram_rom_adr<24>       2       1<- \/4   0     FB6_8   78    I/O     O
rd5                   9       4<-   0   0     FB6_9   79    I/O     O
$OpTx$FX_DC$71        3       0     0   2     FB6_10        (b)     (b)
$OpTx$FX_DC$70        3       0   \/2   0     FB6_11  80    I/O     (b)
rd4                   6       2<- \/1   0     FB6_12  81    I/O     O
$OpTx$FX_DC$30        3       1<- \/3   0     FB6_13        (b)     (b)
$OpTx$FX_DC$84        4       3<- \/4   0     FB6_14  82    I/O     I
ram_ce                6       4<- \/3   0     FB6_15  85    I/O     O
use_cart_logic/oss_bank<0>
                      6       3<- \/2   0     FB6_16        (b)     (b)
use_cart_logic/N19/use_cart_logic/N19_D2
                      7       2<-   0   0     FB6_17  86    I/O     I
use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2
                      1       0   \/4   0     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$19    17: s5                                                                              33: use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2 
  2: $OpTx$FX_DC$22    18: use_cart_logic/N19/use_cart_logic/N19_D2                                        34: use_cart_logic/cfg_enable 
  3: $OpTx$FX_DC$36    19: use_cart_logic/N230/use_cart_logic/N230_D2                                      35: use_cart_logic/cfg_enable2 
  4: $OpTx$FX_DC$7     20: use_cart_logic/N26/use_cart_logic/N26_D2                                        36: use_cart_logic/cfg_mode<0> 
  5: adr<2>            21: use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2                    37: use_cart_logic/cfg_mode<1> 
  6: adr<3>            22: use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2                    38: use_cart_logic/cfg_mode<2> 
  7: adr<7>            23: use_cart_logic/cfg_bank2<15>                                                    39: use_cart_logic/cfg_mode<3> 
  8: cctl              24: use_cart_logic/cfg_bank2<16>                                                    40: use_cart_logic/cfg_mode<4> 
  9: mod_en            25: use_cart_logic/cfg_bank2<23>                                                    41: use_cart_logic/cfg_mode<5> 
 10: data<2>.PIN       26: use_cart_logic/cfg_bank2<24>                                                    42: use_cart_logic/cfg_source_ram 
 11: data<3>.PIN       27: use_cart_logic/cfg_bank<15>                                                     43: use_cart_logic/cfg_source_ram2 
 12: rd4               28: use_cart_logic/cfg_bank<16>                                                     44: use_cart_logic/cfg_write_enable2 
 13: rd5               29: use_cart_logic/cfg_bank<23>                                                     45: use_cart_logic/oss_bank<0> 
 14: reset_n_sync      30: use_cart_logic/cfg_bank<24>                                                     46: use_cart_logic/oss_bank<1> 
 15: rw                31: use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2        47: use_cart_logic/sic_8xxx_enable 
 16: s4                32: use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2  48: use_cart_logic/sic_axxx_enable 

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
$OpTx$BIN_OR$350     .X..XXXX.XX..XX...XXXX.....X..XXX..XXXXXX......... 23
ram_rom_adr<15>      ...X............XX....X...X.........XX.XX......... 9
use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2 
                     ..................X.X..............XXXXX.......... 7
$OpTx$FX_DC$19       ...X...........X.....X................XXX......... 6
ram_rom_adr<16>      X...............X......X...X........XX.XX......... 8
ram_rom_adr<23>      X.......................X...X..................... 3
use_cart_logic/N26/use_cart_logic/N26_D2 
                     ......X..............X.............XX...X......... 5
ram_rom_adr<24>      X........................X...X.................... 3
rd5                  ..X..............................X.XXXXXX...XX.X.. 11
$OpTx$FX_DC$71       ..................X.XX..............XX.XX......... 7
$OpTx$FX_DC$70       ..X....X.....XX...X.X.........XXX...XX.XX......... 13
rd4                  .................................XXXXXXXX.....X... 9
$OpTx$FX_DC$30       .X....XX..........XX...............XXXX........... 9
$OpTx$FX_DC$84       ..X....X.....XX...XXX..........XX...XX.XX......... 13
ram_ce               ........X..XX.XXXX...................X..XXXX...... 12
use_cart_logic/oss_bank<0> 
                     .XX..XX......X....XX...............X.XXX....X..... 12
use_cart_logic/N19/use_cart_logic/N19_D2 
                     ..X............X...................XXXXXX......... 8
use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2 
                     .X....X............................XXXXXX......... 8
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB7  ***********************************
Number of function block inputs used/remaining:               49/5
Number of signals used by logic mapping into function block:  49
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
$OpTx$INV$2           4       4<- /\5   0     FB7_1         (b)     (b)
ram_rom_we            1       0   /\4   0     FB7_2   50    I/O     O
$OpTx$FX_DC$158       3       0   \/2   0     FB7_3         (b)     (b)
use_cart_logic/cfg_bank<18>
                     11       6<-   0   0     FB7_4         (b)     (b)
ram_rom_adr<2>        1       0   /\4   0     FB7_5   52    I/O     O
ram_rom_adr<3>        1       0   \/4   0     FB7_6   53    I/O     O
use_cart_logic/cfg_bank<19>
                     14       9<-   0   0     FB7_7         (b)     (b)
ram_rom_adr<4>        1       1<- /\5   0     FB7_8   54    I/O     O
ram_rom_adr<5>        1       0   /\1   3     FB7_9   55    I/O     O
(unused)              0       0     0   5     FB7_10        (b)     
ram_rom_adr<6>        1       0   \/1   3     FB7_11  56    I/O     O
ram_rom_adr<7>        1       1<- \/5   0     FB7_12  58    I/O     O
use_cart_logic/cfg_bank<17>
                     15      10<-   0   0     FB7_13        (b)     (b)
ram_rom_adr<8>        1       1<- /\5   0     FB7_14  59    I/O     O
ram_rom_adr<18>       3       0   /\1   1     FB7_15  60    I/O     O
(unused)              0       0   \/3   2     FB7_16        (b)     (b)
ram_rom_adr<19>       3       3<- \/5   0     FB7_17  61    I/O     O
$OpTx$BIN_STEP$349   15      10<-   0   0     FB7_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$19    18: adr<6>                                                        34: use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2 
  2: $OpTx$FX_DC$23    19: adr<7>                                                        35: use_cart_logic/cfg_bank2<18> 
  3: $OpTx$FX_DC$30    20: adr<8>                                                        36: use_cart_logic/cfg_bank2<19> 
  4: $OpTx$FX_DC$33    21: cctl                                                          37: use_cart_logic/cfg_bank<13> 
  5: $OpTx$FX_DC$35    22: phi2short                                                     38: use_cart_logic/cfg_bank<17> 
  6: $OpTx$FX_DC$36    23: data<0>.PIN                                                   39: use_cart_logic/cfg_bank<18> 
  7: $OpTx$FX_DC$43    24: data<3>.PIN                                                   40: use_cart_logic/cfg_bank<19> 
  8: $OpTx$FX_DC$71    25: data<4>.PIN                                                   41: use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2 
  9: $OpTx$FX_DC$84    26: data<5>.PIN                                                   42: use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 
 10: $OpTx$FX_DC$9     27: data<6>.PIN                                                   43: use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2 
 11: $OpTx$FX_SC$112   28: reset_n_sync                                                  44: use_cart_logic/cfg_mode<0> 
 12: $OpTx$INV$2       29: rw                                                            45: use_cart_logic/cfg_mode<1> 
 13: adr<0>            30: s5                                                            46: use_cart_logic/cfg_mode<2> 
 14: adr<2>            31: use_cart_logic/N230/use_cart_logic/N230_D2                    47: use_cart_logic/cfg_mode<3> 
 15: adr<3>            32: use_cart_logic/N26/use_cart_logic/N26_D2                      48: use_cart_logic/cfg_mode<4> 
 16: adr<4>            33: use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2  49: use_cart_logic/cfg_mode<5> 
 17: adr<5>           

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
$OpTx$INV$2          ...............XXXX........................XX..... 6
ram_rom_we           .....................X......X..................... 2
$OpTx$FX_DC$158      ................X.X...........X............X..X.X. 6
use_cart_logic/cfg_bank<18> 
                     ....XX.XX.X....XX...X...XX.XX..XX.....X..XXXXX.... 20
ram_rom_adr<2>       .............X.................................... 1
ram_rom_adr<3>       ..............X................................... 1
use_cart_logic/cfg_bank<19> 
                     .....X.X..X.....XX..X....XXXX.XXX......X.X.XXX.XX. 20
ram_rom_adr<4>       ...............X.................................. 1
ram_rom_adr<5>       ................X................................. 1
ram_rom_adr<6>       .................X................................ 1
ram_rom_adr<7>       ..................X............................... 1
use_cart_logic/cfg_bank<17> 
                     ....XX..X.X...XX....X..XX..XX.XXX....X...XXXXX.XX. 22
ram_rom_adr<8>       ...................X.............................. 1
ram_rom_adr<18>      X............................X....X...X.....XX.XX. 8
ram_rom_adr<19>      X............................X.....X...X...XXX.XX. 9
$OpTx$BIN_STEP$349   .XXXXXX..X.XX..XXXX.X.X....XX.XX.X..X...XX.X.XXXX. 28
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB8  ***********************************
Number of function block inputs used/remaining:               45/9
Number of signals used by logic mapping into function block:  45
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
use_cart_logic/cfg_mode<2>
                      5       4<- /\4   0     FB8_1         (b)     (b)
ram_rom_adr<22>       2       1<- /\4   0     FB8_2   63    I/O     O
use_cart_logic/cfg_mode<1>
                      5       1<- /\1   0     FB8_3         (b)     (b)
use_cart_logic/cfg_bank2<23>
                      5       1<- /\1   0     FB8_4         (b)     (b)
ram_rom_adr<21>       2       0   /\1   2     FB8_5   64    I/O     O
ram_rom_adr<20>       2       0     0   3     FB8_6   65    I/O     O
use_cart_logic/cfg_bank2<22>
                      5       0     0   0     FB8_7         (b)     (b)
ram_rom_adr<9>        1       0     0   4     FB8_8   66    I/O     O
ram_rom_adr<10>       1       0   \/1   3     FB8_9   67    I/O     O
use_cart_logic/cfg_bank2<21>
                      5       1<- \/1   0     FB8_10        (b)     (b)
ram_rom_adr<11>       1       1<- \/5   0     FB8_11  68    I/O     O
ram_rom_adr<12>       5       5<- \/5   0     FB8_12  70    I/O     O
use_cart_logic/cfg_mode<0>
                      6       5<- \/4   0     FB8_13        (b)     (b)
ram_rom_adr<13>      12       7<-   0   0     FB8_14  71    I/O     O
ram_rom_adr<14>       3       1<- /\3   0     FB8_15  72    I/O     O
use_cart_logic/cfg_bank<22>
                      6       2<- /\1   0     FB8_16        (b)     (b)
mod_en                6       3<- /\2   0     FB8_17  73    I/O     O
use_cart_logic/cfg_bank<21>
                      6       4<- /\3   0     FB8_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$19              16: mod_en                                                        31: use_cart_logic/cfg_bank2<23> 
  2: $OpTx$FX_DC$23              17: data<0>.PIN                                                   32: use_cart_logic/cfg_bank<13> 
  3: $OpTx$FX_DC$36              18: data<1>.PIN                                                   33: use_cart_logic/cfg_bank<14> 
  4: $OpTx$FX_DC$6               19: data<2>.PIN                                                   34: use_cart_logic/cfg_bank<20> 
  5: $OpTx$FX_DC$7               20: reset_n_sync                                                  35: use_cart_logic/cfg_bank<21> 
  6: adr<0>                      21: s4                                                            36: use_cart_logic/cfg_bank<22> 
  7: adr<10>                     22: s5                                                            37: use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 
  8: adr<11>                     23: use_cart_logic/N19/use_cart_logic/N19_D2                      38: use_cart_logic/cfg_mode<0> 
  9: adr<12>                     24: use_cart_logic/N230/use_cart_logic/N230_D2                    39: use_cart_logic/cfg_mode<1> 
 10: adr<1>                      25: use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2  40: use_cart_logic/cfg_mode<2> 
 11: adr<2>                      26: use_cart_logic/cfg_bank2<13>                                  41: use_cart_logic/cfg_mode<3> 
 12: adr<3>                      27: use_cart_logic/cfg_bank2<14>                                  42: use_cart_logic/cfg_mode<4> 
 13: adr<9>                      28: use_cart_logic/cfg_bank2<20>                                  43: use_cart_logic/cfg_mode<5> 
 14: cctl                        29: use_cart_logic/cfg_bank2<21>                                  44: use_cart_logic/oss_bank<0> 
 15: data_or0000/data_or0000_D2  30: use_cart_logic/cfg_bank2<22>                                  45: use_cart_logic/oss_bank<1> 

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
use_cart_logic/cfg_mode<2> 
                     ...X.X...XXX.XX...XX...X...............X.......... 11
ram_rom_adr<22>      X............................X.....X.............. 3
use_cart_logic/cfg_mode<1> 
                     ...X.X...XXX.XX..X.X...X..............X........... 11
use_cart_logic/cfg_bank2<23> 
                     ...X.X...XXX.XX...XX...X......X.....X............. 12
ram_rom_adr<21>      X...........................X.....X............... 3
ram_rom_adr<20>      X..........................X.....X................ 3
use_cart_logic/cfg_bank2<22> 
                     ...X.X...XXX.XX..X.X...X.....X......X............. 12
ram_rom_adr<9>       ............X..................................... 1
ram_rom_adr<10>      ......X........................................... 1
use_cart_logic/cfg_bank2<21> 
                     ...X.X...XXX.XX.X..X...X....X.......X............. 12
ram_rom_adr<11>      .......X.......................................... 1
ram_rom_adr<12>      ..X.....X.............................XXX..XX..... 7
use_cart_logic/cfg_mode<0> 
                     ...X.X...XXX.XX.X..X...X.............X............ 11
ram_rom_adr<13>      ....X...X...........XXX.XX.....X.....X.XXXXXX..... 15
ram_rom_adr<14>      XX...................X....X.....X........XX....... 7
use_cart_logic/cfg_bank<22> 
                     ...X.X...XXX.XX..X.X...X...........X.............. 11
mod_en               ...X.X...XXX.XXXX..X...X.......................... 11
use_cart_logic/cfg_bank<21> 
                     ...X.X...XXX.XX.X..X...X..........X............... 11
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$BIN_OR$350 <= ((NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(0) AND adr(3) AND reset_n_sync AND 
	use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2 AND NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_bank(16) AND reset_n_sync AND 
	NOT use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2 AND 
	NOT use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	NOT use_cart_logic/cfg_mode(2) AND NOT use_cart_logic/cfg_mode(3) AND adr(3) AND NOT adr(7) AND 
	NOT cctl AND reset_n_sync AND 
	use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2 AND use_cart_logic/N26/use_cart_logic/N26_D2 AND 
	$OpTx$FX_DC$22)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(0) AND NOT use_cart_logic/cfg_mode(1) AND NOT adr(7) AND NOT rw AND 
	data(2).PIN AND NOT cctl AND reset_n_sync AND $OpTx$FX_DC$22)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND adr(2) AND reset_n_sync AND 
	use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2 AND NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(1) AND NOT rw AND NOT cctl AND data(3).PIN AND reset_n_sync AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (NOT use_cart_logic/cfg_mode(1) AND NOT rw AND NOT cctl AND 
	data(3).PIN AND reset_n_sync AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT rw AND NOT cctl AND data(3).PIN AND reset_n_sync AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND use_cart_logic/N26/use_cart_logic/N26_D2 AND 
	NOT $OpTx$FX_DC$22)
	OR (use_cart_logic/cfg_mode(3) AND 
	use_cart_logic/cfg_bank(16) AND rw AND reset_n_sync)
	OR (NOT use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_bank(16) AND rw AND reset_n_sync)
	OR (use_cart_logic/cfg_bank(16) AND rw AND reset_n_sync AND 
	use_cart_logic/N26/use_cart_logic/N26_D2 AND NOT $OpTx$FX_DC$22)
	OR (NOT use_cart_logic/cfg_mode(5) AND 
	use_cart_logic/cfg_bank(16) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND use_cart_logic/N26/use_cart_logic/N26_D2 AND 
	NOT $OpTx$FX_DC$22)
	OR (use_cart_logic/cfg_mode(0) AND 
	use_cart_logic/cfg_mode(1) AND NOT rw AND data(2).PIN AND reset_n_sync AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2));


$OpTx$BIN_STEP$349 <= ((NOT rw AND data(0).PIN AND reset_n_sync AND 
	use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_bank(13) AND reset_n_sync AND 
	NOT use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND NOT rw AND data(0).PIN AND reset_n_sync AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT $OpTx$FX_DC$23)
	OR (NOT use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(3) AND NOT adr(0) AND reset_n_sync AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND $OpTx$INV$2)
	OR (NOT adr(6) AND adr(7) AND NOT rw AND NOT cctl AND data(0).PIN AND 
	reset_n_sync AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (adr(5) AND NOT $OpTx$INV$2 AND $OpTx$FX_DC$33)
	OR (NOT use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(3) AND NOT $OpTx$INV$2 AND $OpTx$FX_DC$43)
	OR (NOT use_cart_logic/cfg_mode(3) AND adr(4) AND 
	use_cart_logic/N26/use_cart_logic/N26_D2 AND $OpTx$FX_DC$33)
	OR (use_cart_logic/cfg_bank(13) AND adr(7) AND 
	NOT $OpTx$INV$2 AND $OpTx$FX_DC$35)
	OR (adr(0) AND reset_n_sync AND $OpTx$FX_DC$36 AND 
	$OpTx$FX_DC$30)
	OR (use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(0) AND $OpTx$FX_DC$43)
	OR (use_cart_logic/cfg_mode(2) AND adr(4) AND 
	$OpTx$FX_DC$43)
	OR (NOT use_cart_logic/cfg_mode(3) AND adr(7) AND 
	$OpTx$FX_DC$33)
	OR (adr(6) AND NOT $OpTx$INV$2 AND $OpTx$FX_DC$33)
	OR (reset_n_sync AND NOT $OpTx$FX_DC$36 AND $OpTx$FX_DC$9));


$OpTx$FX_DC$107 <= ((rw AND reset_n_sync AND 
	use_cart_logic/N145/use_cart_logic/N145_D2)
	OR (use_cart_logic/cfg_mode(4) AND 
	NOT use_cart_logic/cfg_mode(5) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_mode(4) AND reset_n_sync AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (NOT use_cart_logic/cfg_mode(4) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND use_cart_logic/N145/use_cart_logic/N145_D2)
	OR (NOT use_cart_logic/cfg_mode(4) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2 AND 
	NOT use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2));


$OpTx$FX_DC$124 <= (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(3) AND 
	use_cart_logic/cfg_mode(0) AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2 AND $OpTx$FX_DC$23);


$OpTx$FX_DC$137 <= (use_cart_logic/cfg_mode(3) AND adr(3));


$OpTx$FX_DC$158 <= ((use_cart_logic/cfg_mode(3))
	OR (adr(7) AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(0) AND adr(5)));


$OpTx$FX_DC$19 <= (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND NOT use_cart_logic/cfg_mode(3) AND NOT s4 AND 
	NOT use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2 AND $OpTx$FX_DC$7);


$OpTx$FX_DC$22 <= (NOT adr(6) AND NOT adr(5) AND NOT adr(4));


$OpTx$FX_DC$23 <= (use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(1));


$OpTx$FX_DC$30 <= ((NOT use_cart_logic/cfg_mode(3) AND 
	use_cart_logic/cfg_mode(1) AND NOT adr(7) AND NOT cctl AND 
	use_cart_logic/N26/use_cart_logic/N26_D2 AND $OpTx$FX_DC$22)
	OR (use_cart_logic/cfg_mode(0) AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(0) AND NOT adr(7) AND NOT cctl AND $OpTx$FX_DC$22));


$OpTx$FX_DC$33 <= ((reset_n_sync AND $OpTx$FX_DC$9)
	OR (use_cart_logic/cfg_bank(13) AND reset_n_sync AND 
	$OpTx$FX_DC$36 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2));


$OpTx$FX_DC$35 <= ((rw AND reset_n_sync)
	OR (reset_n_sync AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2));


$OpTx$FX_DC$36 <= (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2);


$OpTx$FX_DC$42 <= ((NOT use_cart_logic/cfg_enable AND rw)
	OR (NOT rw AND $OpTx$INV$3));


$OpTx$FX_DC$43 <= ((reset_n_sync AND $OpTx$FX_DC$9)
	OR (use_cart_logic/cfg_bank(13) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND use_cart_logic/N26/use_cart_logic/N26_D2));


$OpTx$FX_DC$56 <= (NOT adr(6) AND NOT adr(7));


$OpTx$FX_DC$6 <= (NOT adr(3) AND NOT rw AND NOT cctl AND 
	use_cart_logic/N230/use_cart_logic/N230_D2);


$OpTx$FX_DC$7 <= (NOT use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(0));


$OpTx$FX_DC$70 <= ((NOT rw AND reset_n_sync AND 
	use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND NOT use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(1) AND NOT rw AND reset_n_sync AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT rw AND NOT cctl AND reset_n_sync AND NOT $OpTx$FX_DC$36 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2));


$OpTx$FX_DC$71 <= ((NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(1) AND NOT use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2));


$OpTx$FX_DC$84 <= ((NOT use_cart_logic/cfg_mode(2) AND NOT rw AND NOT cctl AND 
	reset_n_sync AND NOT $OpTx$FX_DC$36 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (NOT rw AND NOT cctl AND reset_n_sync AND NOT $OpTx$FX_DC$36 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(1) AND NOT rw AND NOT cctl AND reset_n_sync AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (NOT rw AND NOT cctl AND reset_n_sync AND $OpTx$FX_DC$36 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND use_cart_logic/N26/use_cart_logic/N26_D2));


$OpTx$FX_DC$9 <= ((use_cart_logic/cfg_bank(13) AND rw)
	OR (NOT rw AND NOT cctl AND data(0).PIN AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2));


$OpTx$FX_SC$112 <= ((cctl AND reset_n_sync)
	OR (rw AND reset_n_sync AND NOT $OpTx$FX_DC$36));


$OpTx$INV$2 <= ((use_cart_logic/cfg_mode(0) AND 
	use_cart_logic/cfg_mode(1))
	OR (use_cart_logic/cfg_mode(0) AND adr(6) AND adr(7) AND 
	NOT adr(5) AND adr(4))
	OR (use_cart_logic/cfg_mode(1) AND adr(6) AND NOT adr(7) AND 
	adr(5) AND adr(4))
	OR (NOT use_cart_logic/cfg_mode(0) AND 
	NOT use_cart_logic/cfg_mode(1) AND adr(6) AND adr(7) AND adr(5) AND NOT adr(4)));


$OpTx$INV$3 <= ((NOT use_cart_logic/cfg_enable AND adr(1) AND adr(0))
	OR (NOT adr(6) AND NOT adr(3) AND adr(7) AND adr(5) AND adr(1) AND 
	NOT adr(2) AND NOT adr(0) AND NOT adr(4) AND NOT data(0).PIN)
	OR (NOT use_cart_logic/cfg_enable AND adr(2))
	OR (NOT use_cart_logic/cfg_enable AND adr(6))
	OR (NOT use_cart_logic/cfg_enable AND adr(3))
	OR (NOT use_cart_logic/cfg_enable AND NOT adr(7))
	OR (NOT use_cart_logic/cfg_enable AND NOT adr(5))
	OR (NOT use_cart_logic/cfg_enable AND adr(4)));


















data_I(0) <= ((use_cart_logic/cfg_mode(0) AND adr(1) AND adr(2) AND 
	NOT adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank2(13) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank2(21) AND NOT adr(1) AND adr(2) AND 
	NOT adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank(21) AND NOT adr(1) AND NOT adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2)
	OR (adr(1) AND adr(2) AND adr(0) AND NOT mod_en AND 
	data_or0000/data_or0000_D2)
	OR (ram_rom_data(0).PIN AND NOT data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank(13) AND 
	data_or0000/data_or0000_D2 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_enable AND adr(1) AND NOT adr(2) AND 
	NOT adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_enable2 AND NOT adr(1) AND adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2));
data(0) <= data_I(0) when data_OE(0) = '1' else 'Z';
data_OE(0) <= data_1_IOBUFE/data_1_IOBUFE_TRST;


data_I(1) <= ((use_cart_logic/cfg_mode(1) AND adr(1) AND adr(2) AND 
	NOT adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank2(14) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_source_ram AND adr(1) AND adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2)
	OR (ram_rom_data(1).PIN AND NOT data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank(14) AND 
	data_or0000/data_or0000_D2 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_bank2(22) AND NOT adr(1) AND adr(2) AND 
	NOT adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank(22) AND NOT adr(1) AND NOT adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2));
data(1) <= data_I(1) when data_OE(1) = '1' else 'Z';
data_OE(1) <= data_1_IOBUFE/data_1_IOBUFE_TRST;


data_I(2) <= ((use_cart_logic/cfg_mode(2) AND adr(1) AND adr(2) AND 
	NOT adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank2(15) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_write_enable2 AND adr(1) AND 
	adr(2) AND adr(0) AND data_or0000/data_or0000_D2)
	OR (ram_rom_data(2).PIN AND NOT data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank(15) AND 
	data_or0000/data_or0000_D2 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_bank2(23) AND NOT adr(1) AND adr(2) AND 
	NOT adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank(23) AND NOT adr(1) AND NOT adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2));
data(2) <= data_I(2) when data_OE(2) = '1' else 'Z';
data_OE(2) <= data_1_IOBUFE/data_1_IOBUFE_TRST;


data_I(3) <= ((use_cart_logic/cfg_mode(3) AND adr(1) AND adr(2) AND 
	NOT adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank2(16) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_source_ram2 AND adr(1) AND adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2)
	OR (ram_rom_data(3).PIN AND NOT data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank(16) AND 
	data_or0000/data_or0000_D2 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_bank2(24) AND NOT adr(1) AND adr(2) AND 
	NOT adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank(24) AND NOT adr(1) AND NOT adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2));
data(3) <= data_I(3) when data_OE(3) = '1' else 'Z';
data_OE(3) <= data_1_IOBUFE/data_1_IOBUFE_TRST;


data_I(4) <= ((use_cart_logic/cfg_mode(4) AND adr(1) AND adr(2) AND 
	NOT adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank2(17) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank2(25) AND NOT adr(1) AND adr(2) AND 
	NOT adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank(25) AND NOT adr(1) AND NOT adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2)
	OR (ram_rom_data(4).PIN AND NOT data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank(17) AND 
	data_or0000/data_or0000_D2 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2));
data(4) <= data_I(4) when data_OE(4) = '1' else 'Z';
data_OE(4) <= data_1_IOBUFE/data_1_IOBUFE_TRST;


data_I(5) <= ((use_cart_logic/cfg_mode(5) AND adr(1) AND adr(2) AND 
	NOT adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank2(18) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank2(26) AND NOT adr(1) AND adr(2) AND 
	NOT adr(0) AND data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank(26) AND NOT adr(1) AND NOT adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2)
	OR (ram_rom_data(5).PIN AND NOT data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank(18) AND 
	data_or0000/data_or0000_D2 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2));
data(5) <= data_I(5) when data_OE(5) = '1' else 'Z';
data_OE(5) <= data_1_IOBUFE/data_1_IOBUFE_TRST;


data_I(6) <= ((ram_rom_data(6).PIN AND NOT data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank(19) AND 
	data_or0000/data_or0000_D2 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_bank2(19) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2));
data(6) <= data_I(6) when data_OE(6) = '1' else 'Z';
data_OE(6) <= data_1_IOBUFE/data_1_IOBUFE_TRST;


data_I(7) <= ((use_cart_logic/cfg_bank2(20) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND data_or0000/data_or0000_D2)
	OR (ram_rom_data(7).PIN AND NOT data_or0000/data_or0000_D2)
	OR (use_cart_logic/cfg_bank(20) AND 
	data_or0000/data_or0000_D2 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (adr(3) AND eeprom_so AND data_or0000/data_or0000_D2));
data(7) <= data_I(7) when data_OE(7) = '1' else 'Z';
data_OE(7) <= data_1_IOBUFE/data_1_IOBUFE_TRST;


data_1_IOBUFE/data_1_IOBUFE_TRST <= ((data_or0000/data_or0000_D2)
	OR (NOT s4 AND rw AND rd4)
	OR (rw AND NOT s5 AND rd5 AND 
	use_cart_logic/N19/use_cart_logic/N19_D2));


data_or0000/data_or0000_D2 <= ((NOT adr(3) AND rw AND NOT cctl AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT adr(1) AND NOT adr(2) AND rw AND NOT adr(0) AND NOT cctl AND 
	use_cart_logic/N230/use_cart_logic/N230_D2));

FTCPE_eeprom_cs: FTCPE port map (eeprom_cs,eeprom_cs_T,NOT phi2short,'0','0');
eeprom_cs_T <= ((adr(3) AND NOT adr(1) AND NOT adr(2) AND NOT rw AND NOT adr(0) AND NOT cctl AND 
	eeprom_cs AND NOT data(1).PIN AND reset_n AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (adr(3) AND NOT adr(1) AND NOT adr(2) AND NOT rw AND NOT adr(0) AND NOT cctl AND 
	eeprom_cs AND reset_n AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (NOT eeprom_cs AND NOT reset_n)
	OR (NOT adr(1) AND NOT adr(2) AND NOT rw AND NOT adr(0) AND NOT cctl AND 
	NOT eeprom_cs AND data(1).PIN AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2));

FTCPE_eeprom_sck: FTCPE port map (eeprom_sck,eeprom_sck_T,NOT phi2short,'0','0');
eeprom_sck_T <= ((adr(3) AND NOT adr(1) AND NOT adr(2) AND NOT rw AND NOT adr(0) AND NOT cctl AND 
	eeprom_sck AND NOT data(0).PIN AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (adr(3) AND NOT adr(1) AND NOT adr(2) AND NOT rw AND NOT adr(0) AND NOT cctl AND 
	eeprom_sck AND use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (NOT adr(1) AND NOT adr(2) AND NOT rw AND NOT adr(0) AND NOT cctl AND 
	NOT eeprom_sck AND data(0).PIN AND reset_n AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (eeprom_sck AND NOT reset_n));

FTCPE_eeprom_si: FTCPE port map (eeprom_si,eeprom_si_T,NOT phi2short,'0','0');
eeprom_si_T <= ((adr(3) AND NOT adr(1) AND NOT adr(2) AND NOT rw AND NOT adr(0) AND NOT cctl AND 
	eeprom_si AND NOT data(7).PIN AND reset_n AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (adr(3) AND NOT adr(1) AND NOT adr(2) AND NOT rw AND NOT adr(0) AND NOT cctl AND 
	eeprom_si AND reset_n AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (NOT eeprom_si AND NOT reset_n)
	OR (NOT adr(1) AND NOT adr(2) AND NOT rw AND NOT adr(0) AND NOT cctl AND 
	NOT eeprom_si AND data(7).PIN AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2));

FDCPE_mod_en: FDCPE port map (mod_en,mod_en_D,NOT phi2short,'0','0');
mod_en_D <= ((NOT reset_n_sync)
	OR (NOT adr(0) AND mod_en)
	OR (mod_en AND NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND adr(1) AND adr(2) AND adr(0) AND NOT cctl AND 
	NOT data(0).PIN AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT adr(1) AND mod_en)
	OR (NOT adr(2) AND mod_en));


ram_ce <= NOT (((use_cart_logic/cfg_source_ram AND rw AND NOT s5 AND rd5 AND 
	use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (use_cart_logic/cfg_source_ram AND NOT s5 AND rd5 AND 
	NOT mod_en AND use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(2) AND NOT s4 AND use_cart_logic/cfg_source_ram2 AND 
	use_cart_logic/cfg_write_enable2 AND rd4 AND NOT use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(2) AND NOT s4 AND use_cart_logic/cfg_source_ram2 AND rw AND rd4 AND 
	NOT use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (NOT s4 AND use_cart_logic/cfg_source_ram AND rw AND rd4 AND 
	use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (NOT s4 AND use_cart_logic/cfg_source_ram AND rd4 AND 
	NOT mod_en AND use_cart_logic/N19/use_cart_logic/N19_D2)));


ram_rom_adr(0) <= adr(0);


ram_rom_adr(1) <= adr(1);


ram_rom_adr(2) <= adr(2);


ram_rom_adr(3) <= adr(3);


ram_rom_adr(4) <= adr(4);


ram_rom_adr(5) <= adr(5);


ram_rom_adr(6) <= adr(6);


ram_rom_adr(7) <= adr(7);


ram_rom_adr(8) <= adr(8);


ram_rom_adr(9) <= adr(9);


ram_rom_adr(10) <= adr(10);


ram_rom_adr(11) <= adr(11);


ram_rom_adr(12) <= ((use_cart_logic/cfg_mode(3) AND adr(12))
	OR (use_cart_logic/cfg_mode(1) AND adr(12))
	OR (adr(12) AND NOT $OpTx$FX_DC$36)
	OR (NOT use_cart_logic/oss_bank(0) AND 
	NOT use_cart_logic/oss_bank(1) AND adr(12))
	OR (use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(3) AND use_cart_logic/oss_bank(0) AND NOT adr(12) AND 
	$OpTx$FX_DC$36));


ram_rom_adr(13) <= ((NOT use_cart_logic/cfg_mode(5) AND 
	use_cart_logic/cfg_mode(3) AND use_cart_logic/cfg_bank(13))
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(3) AND s4)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND s4 AND 
	use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2)
	OR (NOT use_cart_logic/cfg_mode(5) AND 
	use_cart_logic/cfg_bank(13) AND NOT use_cart_logic/oss_bank(0) AND 
	NOT use_cart_logic/oss_bank(1))
	OR (use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(2) AND use_cart_logic/cfg_bank2(13) AND 
	NOT use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND s4 AND use_cart_logic/N19/use_cart_logic/N19_D2 AND 
	NOT $OpTx$FX_DC$7)
	OR (use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(0) AND use_cart_logic/oss_bank(1) AND NOT adr(12) AND 
	use_cart_logic/N19/use_cart_logic/N19_D2 AND 
	use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_bank(13))
	OR (use_cart_logic/cfg_mode(4) AND NOT s5 AND 
	use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (NOT use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(2) AND use_cart_logic/cfg_bank(13))
	OR (use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_bank(13) AND NOT use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (s4 AND use_cart_logic/cfg_bank(13) AND 
	NOT use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2));


ram_rom_adr(14) <= ((use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND NOT s5 AND NOT $OpTx$FX_DC$23)
	OR (use_cart_logic/cfg_bank(14) AND NOT $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_bank2(14) AND $OpTx$FX_DC$19));


ram_rom_adr(15) <= ((NOT use_cart_logic/cfg_mode(5) AND 
	use_cart_logic/cfg_bank(15))
	OR (use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_bank(15))
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(1) AND NOT s5 AND use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (use_cart_logic/cfg_mode(4) AND NOT s5 AND 
	use_cart_logic/N19/use_cart_logic/N19_D2 AND NOT $OpTx$FX_DC$7)
	OR (use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(2) AND use_cart_logic/cfg_bank2(15) AND 
	NOT use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (use_cart_logic/cfg_bank(15) AND 
	use_cart_logic/N19/use_cart_logic/N19_D2));


ram_rom_adr(16) <= ((use_cart_logic/cfg_bank(16) AND NOT $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_bank2(16) AND $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(1) AND NOT s5)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND NOT use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(1) AND NOT s5));


ram_rom_adr(17) <= ((use_cart_logic/cfg_bank(17) AND NOT $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_bank2(17) AND $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(1) AND NOT s5)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND NOT use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(0) AND use_cart_logic/cfg_mode(1) AND NOT s5));


ram_rom_adr(18) <= ((use_cart_logic/cfg_bank(18) AND NOT $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_bank2(18) AND $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(1) AND NOT s5));


ram_rom_adr(19) <= ((use_cart_logic/cfg_bank(19) AND NOT $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_bank2(19) AND $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(0) AND NOT use_cart_logic/cfg_mode(1) AND NOT s5));


ram_rom_adr(20) <= ((use_cart_logic/cfg_bank(20) AND NOT $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_bank2(20) AND $OpTx$FX_DC$19));


ram_rom_adr(21) <= ((use_cart_logic/cfg_bank2(21) AND $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_bank(21) AND NOT $OpTx$FX_DC$19));


ram_rom_adr(22) <= ((use_cart_logic/cfg_bank2(22) AND $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_bank(22) AND NOT $OpTx$FX_DC$19));


ram_rom_adr(23) <= ((use_cart_logic/cfg_bank2(23) AND $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_bank(23) AND NOT $OpTx$FX_DC$19));


ram_rom_adr(24) <= ((use_cart_logic/cfg_bank2(24) AND $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_bank(24) AND NOT $OpTx$FX_DC$19));


ram_rom_adr(25) <= ((use_cart_logic/cfg_bank2(25) AND $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_bank(25) AND NOT $OpTx$FX_DC$19));


ram_rom_adr(26) <= ((use_cart_logic/cfg_bank2(26) AND $OpTx$FX_DC$19)
	OR (use_cart_logic/cfg_bank(26) AND NOT $OpTx$FX_DC$19));


ram_rom_data_I(0) <= data(0).PIN;
ram_rom_data(0) <= ram_rom_data_I(0) when ram_rom_data_OE(0) = '1' else 'Z';
ram_rom_data_OE(0) <= NOT rw;


ram_rom_data_I(1) <= data(1).PIN;
ram_rom_data(1) <= ram_rom_data_I(1) when ram_rom_data_OE(1) = '1' else 'Z';
ram_rom_data_OE(1) <= NOT rw;


ram_rom_data_I(2) <= data(2).PIN;
ram_rom_data(2) <= ram_rom_data_I(2) when ram_rom_data_OE(2) = '1' else 'Z';
ram_rom_data_OE(2) <= NOT rw;


ram_rom_data_I(3) <= data(3).PIN;
ram_rom_data(3) <= ram_rom_data_I(3) when ram_rom_data_OE(3) = '1' else 'Z';
ram_rom_data_OE(3) <= NOT rw;


ram_rom_data_I(4) <= data(4).PIN;
ram_rom_data(4) <= ram_rom_data_I(4) when ram_rom_data_OE(4) = '1' else 'Z';
ram_rom_data_OE(4) <= NOT rw;


ram_rom_data_I(5) <= data(5).PIN;
ram_rom_data(5) <= ram_rom_data_I(5) when ram_rom_data_OE(5) = '1' else 'Z';
ram_rom_data_OE(5) <= NOT rw;


ram_rom_data_I(6) <= data(6).PIN;
ram_rom_data(6) <= ram_rom_data_I(6) when ram_rom_data_OE(6) = '1' else 'Z';
ram_rom_data_OE(6) <= NOT rw;


ram_rom_data_I(7) <= data(7).PIN;
ram_rom_data(7) <= ram_rom_data_I(7) when ram_rom_data_OE(7) = '1' else 'Z';
ram_rom_data_OE(7) <= NOT rw;


ram_rom_oe <= NOT ((rw AND phi2));


ram_rom_we <= NOT ((phi2short AND NOT rw));


rd4 <= ((use_cart_logic/cfg_mode(5) AND 
	use_cart_logic/cfg_mode(2) AND NOT use_cart_logic/cfg_mode(0) AND 
	NOT use_cart_logic/cfg_mode(1) AND use_cart_logic/cfg_enable AND 
	use_cart_logic/sic_8xxx_enable)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND NOT use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(3) AND NOT use_cart_logic/cfg_mode(0) AND 
	NOT use_cart_logic/cfg_mode(1) AND use_cart_logic/cfg_enable2)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND NOT use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_enable)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(3) AND 
	use_cart_logic/cfg_enable)
	OR (use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(2) AND use_cart_logic/cfg_mode(0) AND 
	use_cart_logic/cfg_enable)
	OR (use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(2) AND use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_enable));


rd5 <= ((NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(3) AND 
	use_cart_logic/cfg_enable)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(3) AND NOT use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_enable)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	NOT use_cart_logic/cfg_mode(2) AND NOT use_cart_logic/cfg_mode(3) AND 
	use_cart_logic/cfg_mode(0) AND use_cart_logic/cfg_enable)
	OR (use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(0) AND NOT use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_enable AND use_cart_logic/sic_axxx_enable)
	OR (use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(2) AND use_cart_logic/cfg_enable)
	OR (use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_enable AND $OpTx$FX_DC$36)
	OR (use_cart_logic/cfg_enable AND 
	use_cart_logic/oss_bank(0) AND $OpTx$FX_DC$36)
	OR (use_cart_logic/cfg_enable AND 
	use_cart_logic/oss_bank(1) AND $OpTx$FX_DC$36)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND NOT use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_enable));

FDCPE_reset_n_sync: FDCPE port map (reset_n_sync,reset_n_sync1,NOT phi2short,'0','0');

FDCPE_reset_n_sync1: FDCPE port map (reset_n_sync1,reset_n,NOT phi2short,'0','0');


rom_ce <= NOT (((NOT s4 AND NOT use_cart_logic/cfg_source_ram AND rw AND rd4 AND 
	use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (NOT s4 AND NOT use_cart_logic/cfg_source_ram AND rd4 AND 
	NOT mod_en AND use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (NOT use_cart_logic/cfg_source_ram AND rw AND NOT s5 AND rd5 AND 
	use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (NOT use_cart_logic/cfg_source_ram AND NOT s5 AND rd5 AND 
	NOT mod_en AND use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(2) AND NOT s4 AND NOT use_cart_logic/cfg_source_ram2 AND 
	use_cart_logic/cfg_write_enable2 AND rd4 AND NOT use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (NOT use_cart_logic/cfg_mode(5) AND NOT s4 AND rw AND rd4 AND 
	NOT use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (use_cart_logic/cfg_mode(2) AND NOT s4 AND rw AND rd4 AND 
	NOT use_cart_logic/N19/use_cart_logic/N19_D2)
	OR (NOT s4 AND NOT use_cart_logic/cfg_source_ram2 AND rw AND rd4 AND 
	NOT use_cart_logic/N19/use_cart_logic/N19_D2)));

FDCPE_rom_reset: FDCPE port map (rom_reset,'1',NOT phi2short,'0','0',reset_n_sync);


use_cart_logic/N145/use_cart_logic/N145_D2 <= ((adr(7) AND 
	use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2 AND NOT $OpTx$INV$2)
	OR (adr(5) AND use_cart_logic/N26/use_cart_logic/N26_D2 AND 
	NOT $OpTx$INV$2)
	OR (adr(4) AND use_cart_logic/N26/use_cart_logic/N26_D2 AND 
	NOT $OpTx$INV$2)
	OR (NOT use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(3) AND 
	use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2 AND NOT $OpTx$INV$2)
	OR (use_cart_logic/cfg_mode(2) AND adr(6) AND 
	use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2)
	OR (NOT use_cart_logic/cfg_mode(3) AND adr(6) AND 
	use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT use_cart_logic/cfg_mode(3) AND 
	use_cart_logic/N26/use_cart_logic/N26_D2 AND NOT $OpTx$FX_DC$7));


use_cart_logic/N19/use_cart_logic/N19_D2 <= (($OpTx$FX_DC$36)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(2) AND NOT use_cart_logic/cfg_mode(0) AND 
	NOT use_cart_logic/cfg_mode(1))
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	NOT use_cart_logic/cfg_mode(2) AND use_cart_logic/cfg_mode(0) AND 
	NOT use_cart_logic/cfg_mode(1))
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND NOT use_cart_logic/cfg_mode(1))
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(3))
	OR (use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(2) AND use_cart_logic/cfg_mode(1))
	OR (use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(2) AND s4));


use_cart_logic/N230/use_cart_logic/N230_D2 <= ((cctl)
	OR (NOT adr(6) AND adr(7) AND adr(5) AND NOT adr(4)));


use_cart_logic/N26/use_cart_logic/N26_D2 <= ((NOT use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2)
	OR (adr(7) AND 
	use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2)
	OR (NOT use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(0) AND 
	use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2));


use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2 <= (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(3) AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2);


use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2 <= ((NOT use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(2) AND use_cart_logic/cfg_mode(3) AND 
	NOT use_cart_logic/cfg_mode(0))
	OR (NOT use_cart_logic/cfg_mode(5) AND 
	NOT use_cart_logic/cfg_mode(2) AND NOT use_cart_logic/cfg_mode(3) AND 
	use_cart_logic/cfg_mode(1))
	OR (NOT use_cart_logic/cfg_mode(5) AND 
	use_cart_logic/cfg_mode(3) AND use_cart_logic/cfg_mode(0) AND 
	NOT use_cart_logic/cfg_mode(1))
	OR (NOT use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(3) AND NOT use_cart_logic/cfg_mode(0) AND 
	use_cart_logic/cfg_mode(1))
	OR (NOT use_cart_logic/cfg_mode(5) AND 
	use_cart_logic/cfg_mode(2) AND NOT use_cart_logic/cfg_mode(3) AND 
	NOT use_cart_logic/cfg_mode(0) AND NOT use_cart_logic/cfg_mode(1)));

FTCPE_use_cart_logic/cfg_bank213: FTCPE port map (use_cart_logic/cfg_bank2(13),use_cart_logic/cfg_bank2_T(13),NOT phi2short,'0','0');
use_cart_logic/cfg_bank2_T(13) <= ((use_cart_logic/cfg_bank2(13) AND NOT reset_n_sync)
	OR (use_cart_logic/cfg_bank2(13) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND NOT data(0).PIN AND $OpTx$FX_DC$6)
	OR (NOT use_cart_logic/cfg_bank2(13) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND data(0).PIN AND reset_n_sync AND $OpTx$FX_DC$6));

FTCPE_use_cart_logic/cfg_bank214: FTCPE port map (use_cart_logic/cfg_bank2(14),use_cart_logic/cfg_bank2_T(14),NOT phi2short,'0','0');
use_cart_logic/cfg_bank2_T(14) <= ((use_cart_logic/cfg_bank2(14) AND NOT reset_n_sync)
	OR (use_cart_logic/cfg_bank2(14) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND NOT data(1).PIN AND $OpTx$FX_DC$6)
	OR (NOT use_cart_logic/cfg_bank2(14) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND data(1).PIN AND reset_n_sync AND $OpTx$FX_DC$6));

FTCPE_use_cart_logic/cfg_bank215: FTCPE port map (use_cart_logic/cfg_bank2(15),use_cart_logic/cfg_bank2_T(15),NOT phi2short,'0','0');
use_cart_logic/cfg_bank2_T(15) <= ((use_cart_logic/cfg_bank2(15) AND NOT reset_n_sync)
	OR (use_cart_logic/cfg_bank2(15) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND NOT data(2).PIN AND $OpTx$FX_DC$6)
	OR (NOT use_cart_logic/cfg_bank2(15) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND data(2).PIN AND reset_n_sync AND $OpTx$FX_DC$6));

FTCPE_use_cart_logic/cfg_bank216: FTCPE port map (use_cart_logic/cfg_bank2(16),use_cart_logic/cfg_bank2_T(16),NOT phi2short,'0','0');
use_cart_logic/cfg_bank2_T(16) <= ((use_cart_logic/cfg_bank2(16) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND NOT data(3).PIN AND $OpTx$FX_DC$6)
	OR (NOT use_cart_logic/cfg_bank2(16) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND data(3).PIN AND reset_n_sync AND $OpTx$FX_DC$6)
	OR (use_cart_logic/cfg_bank2(16) AND NOT reset_n_sync));

FTCPE_use_cart_logic/cfg_bank217: FTCPE port map (use_cart_logic/cfg_bank2(17),use_cart_logic/cfg_bank2_T(17),NOT phi2short,'0','0');
use_cart_logic/cfg_bank2_T(17) <= ((use_cart_logic/cfg_bank2(17) AND NOT reset_n_sync)
	OR (use_cart_logic/cfg_bank2(17) AND adr(1) AND NOT adr(2) AND 
	NOT data(4).PIN AND adr(0) AND $OpTx$FX_DC$6)
	OR (NOT use_cart_logic/cfg_bank2(17) AND adr(1) AND NOT adr(2) AND 
	data(4).PIN AND adr(0) AND reset_n_sync AND $OpTx$FX_DC$6));

FTCPE_use_cart_logic/cfg_bank218: FTCPE port map (use_cart_logic/cfg_bank2(18),use_cart_logic/cfg_bank2_T(18),NOT phi2short,'0','0');
use_cart_logic/cfg_bank2_T(18) <= ((use_cart_logic/cfg_bank2(18) AND NOT reset_n_sync)
	OR (use_cart_logic/cfg_bank2(18) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND NOT data(5).PIN AND $OpTx$FX_DC$6)
	OR (NOT use_cart_logic/cfg_bank2(18) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND data(5).PIN AND reset_n_sync AND $OpTx$FX_DC$6));

FTCPE_use_cart_logic/cfg_bank219: FTCPE port map (use_cart_logic/cfg_bank2(19),use_cart_logic/cfg_bank2_T(19),NOT phi2short,'0','0');
use_cart_logic/cfg_bank2_T(19) <= ((use_cart_logic/cfg_bank2(19) AND NOT reset_n_sync)
	OR (use_cart_logic/cfg_bank2(19) AND adr(1) AND NOT adr(2) AND 
	NOT data(6).PIN AND adr(0) AND $OpTx$FX_DC$6)
	OR (NOT use_cart_logic/cfg_bank2(19) AND adr(1) AND NOT adr(2) AND 
	data(6).PIN AND adr(0) AND reset_n_sync AND $OpTx$FX_DC$6));

FTCPE_use_cart_logic/cfg_bank220: FTCPE port map (use_cart_logic/cfg_bank2(20),use_cart_logic/cfg_bank2_T(20),NOT phi2short,'0','0');
use_cart_logic/cfg_bank2_T(20) <= ((use_cart_logic/cfg_bank2(20) AND NOT reset_n_sync)
	OR (use_cart_logic/cfg_bank2(20) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND NOT data(7).PIN AND $OpTx$FX_DC$6)
	OR (NOT use_cart_logic/cfg_bank2(20) AND adr(1) AND NOT adr(2) AND 
	adr(0) AND data(7).PIN AND reset_n_sync AND $OpTx$FX_DC$6));

FDCPE_use_cart_logic/cfg_bank221: FDCPE port map (use_cart_logic/cfg_bank2(21),use_cart_logic/cfg_bank2_D(21),NOT phi2short,'0','0');
use_cart_logic/cfg_bank2_D(21) <= ((use_cart_logic/cfg_bank2(21) AND adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(21) AND NOT adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(21) AND adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(21) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND NOT adr(1) AND NOT adr(0) AND NOT cctl AND data(0).PIN AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2));

FDCPE_use_cart_logic/cfg_bank222: FDCPE port map (use_cart_logic/cfg_bank2(22),use_cart_logic/cfg_bank2_D(22),NOT phi2short,'0','0');
use_cart_logic/cfg_bank2_D(22) <= ((use_cart_logic/cfg_bank2(22) AND adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(22) AND NOT adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(22) AND adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(22) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND NOT adr(1) AND NOT adr(0) AND NOT cctl AND data(1).PIN AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2));

FDCPE_use_cart_logic/cfg_bank223: FDCPE port map (use_cart_logic/cfg_bank2(23),use_cart_logic/cfg_bank2_D(23),NOT phi2short,'0','0');
use_cart_logic/cfg_bank2_D(23) <= ((use_cart_logic/cfg_bank2(23) AND adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(23) AND NOT adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(23) AND adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(23) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND NOT adr(1) AND NOT adr(0) AND data(2).PIN AND NOT cctl AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2));

FDCPE_use_cart_logic/cfg_bank224: FDCPE port map (use_cart_logic/cfg_bank2(24),use_cart_logic/cfg_bank2_D(24),NOT phi2short,'0','0');
use_cart_logic/cfg_bank2_D(24) <= ((use_cart_logic/cfg_bank2(24) AND adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(24) AND adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(24) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND NOT adr(1) AND NOT adr(0) AND NOT cctl AND data(3).PIN AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_bank2(24) AND NOT adr(2) AND 
	reset_n_sync));

FDCPE_use_cart_logic/cfg_bank225: FDCPE port map (use_cart_logic/cfg_bank2(25),use_cart_logic/cfg_bank2_D(25),NOT phi2short,'0','0');
use_cart_logic/cfg_bank2_D(25) <= ((use_cart_logic/cfg_bank2(25) AND adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(25) AND adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(25) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND NOT adr(1) AND data(4).PIN AND NOT adr(0) AND NOT cctl AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_bank2(25) AND NOT adr(2) AND 
	reset_n_sync));

FDCPE_use_cart_logic/cfg_bank226: FDCPE port map (use_cart_logic/cfg_bank2(26),use_cart_logic/cfg_bank2_D(26),NOT phi2short,'0','0');
use_cart_logic/cfg_bank2_D(26) <= ((use_cart_logic/cfg_bank2(26) AND adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(26) AND adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank2(26) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND NOT adr(1) AND NOT adr(0) AND NOT cctl AND data(5).PIN AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_bank2(26) AND NOT adr(2) AND 
	reset_n_sync));

FDCPE_use_cart_logic/cfg_bank13: FDCPE port map (use_cart_logic/cfg_bank(13),use_cart_logic/cfg_bank_D(13),NOT phi2short,'0','0');
use_cart_logic/cfg_bank_D(13) <= (($OpTx$BIN_STEP$349)
	OR (use_cart_logic/cfg_mode(4) AND 
	NOT use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_bank(13) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_mode(5) AND $OpTx$FX_DC$33)
	OR (use_cart_logic/cfg_bank(13) AND cctl AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(13) AND reset_n_sync AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_bank(13) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND $OpTx$FX_DC$23));

FDCPE_use_cart_logic/cfg_bank14: FDCPE port map (use_cart_logic/cfg_bank(14),use_cart_logic/cfg_bank_D(14),NOT phi2short,'0','0');
use_cart_logic/cfg_bank_D(14) <= ((use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND NOT rw AND data(1).PIN AND reset_n_sync AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT $OpTx$FX_DC$23)
	OR (NOT use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(3) AND NOT adr(1) AND reset_n_sync AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND $OpTx$INV$2)
	OR (NOT use_cart_logic/cfg_mode(1) AND NOT rw AND data(1).PIN AND 
	reset_n_sync AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND $OpTx$FX_DC$7 AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2)
	OR (rom_ce_OBUF.EXP)
	OR (use_cart_logic/cfg_mode(1) AND NOT rw AND data(0).PIN AND 
	reset_n_sync AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2)
	OR (NOT rw AND data(0).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$7 AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2)
	OR (NOT use_cart_logic/cfg_mode(0) AND adr(0) AND 
	reset_n_sync AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_bank(14) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND $OpTx$FX_DC$7 AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2)
	OR (NOT rw AND NOT cctl AND data(1).PIN AND reset_n_sync AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND use_cart_logic/N145/use_cart_logic/N145_D2)
	OR (use_cart_logic/cfg_bank(14) AND $OpTx$FX_SC$112)
	OR (use_cart_logic/cfg_bank(14) AND $OpTx$FX_DC$107)
	OR (adr(1) AND reset_n_sync AND $OpTx$FX_DC$36 AND 
	$OpTx$FX_DC$30)
	OR (use_cart_logic/cfg_bank(14) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2 AND $OpTx$FX_DC$23)
	OR (NOT rw AND NOT cctl AND data(0).PIN AND reset_n_sync AND 
	use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2));

FDCPE_use_cart_logic/cfg_bank15: FDCPE port map (use_cart_logic/cfg_bank(15),use_cart_logic/cfg_bank_D(15),NOT phi2short,'0','0');
use_cart_logic/cfg_bank_D(15) <= ((use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(2) AND use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_bank(15) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (NOT use_cart_logic/cfg_mode(0) AND adr(1) AND 
	reset_n_sync AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_bank(15) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND NOT use_cart_logic/N26/use_cart_logic/N26_D2 AND 
	$OpTx$FX_DC$7)
	OR (NOT rw AND data(2).PIN AND NOT cctl AND reset_n_sync AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND use_cart_logic/N145/use_cart_logic/N145_D2)
	OR (NOT use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(3) AND NOT adr(2) AND reset_n_sync AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND $OpTx$INV$2)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND NOT use_cart_logic/cfg_mode(1) AND NOT rw AND data(2).PIN AND 
	reset_n_sync AND NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT $OpTx$FX_DC$7)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(3) AND NOT rw AND data(1).PIN AND reset_n_sync AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(3) AND 
	use_cart_logic/cfg_mode(1) AND NOT rw AND data(1).PIN AND reset_n_sync AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(1) AND NOT rw AND data(2).PIN AND reset_n_sync AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND NOT use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND NOT use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(3) AND NOT use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_bank(15) AND reset_n_sync AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_bank(15) AND $OpTx$FX_SC$112)
	OR (use_cart_logic/cfg_bank(15) AND $OpTx$FX_DC$107)
	OR (data(2).PIN AND $OpTx$FX_DC$70)
	OR (adr(2) AND reset_n_sync AND $OpTx$FX_DC$36 AND 
	$OpTx$FX_DC$30)
	OR (NOT rw AND NOT cctl AND data(1).PIN AND reset_n_sync AND 
	use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2));

FDCPE_use_cart_logic/cfg_bank16: FDCPE port map (use_cart_logic/cfg_bank(16),use_cart_logic/cfg_bank_D(16),NOT phi2short,'0','0');
use_cart_logic/cfg_bank_D(16) <= (($OpTx$BIN_OR$350)
	OR (use_cart_logic/cfg_mode(4) AND 
	NOT use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_bank(16) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_mode(2) AND NOT rw AND data(2).PIN AND 
	reset_n_sync AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2)
	OR (NOT use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(1) AND use_cart_logic/cfg_bank(16) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (NOT use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_bank(16) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(3) AND use_cart_logic/cfg_bank(16) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND $OpTx$FX_DC$7)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(2) AND use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_bank(16) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_mode(3) AND NOT rw AND NOT cctl AND 
	data(3).PIN AND reset_n_sync AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND $OpTx$FX_DC$7)
	OR (adr(7) AND NOT rw AND NOT cctl AND data(3).PIN AND 
	reset_n_sync AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(1) AND NOT rw AND data(3).PIN AND reset_n_sync AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (use_cart_logic/cfg_bank(16) AND $OpTx$FX_SC$112)
	OR (data(3).PIN AND $OpTx$FX_DC$70)
	OR (use_cart_logic/cfg_bank(16) AND adr(7) AND 
	$OpTx$FX_DC$35)
	OR (use_cart_logic/cfg_bank(16) AND reset_n_sync AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2));

FDCPE_use_cart_logic/cfg_bank17: FDCPE port map (use_cart_logic/cfg_bank(17),use_cart_logic/cfg_bank_D(17),NOT phi2short,'0','0');
use_cart_logic/cfg_bank_D(17) <= ((NOT use_cart_logic/cfg_mode(5) AND 
	use_cart_logic/cfg_bank(17) AND reset_n_sync AND NOT $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (NOT use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(1) AND use_cart_logic/cfg_bank(17) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (NOT use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_bank(17) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (use_cart_logic/cfg_mode(0) AND NOT cctl AND adr(4) AND 
	reset_n_sync AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT use_cart_logic/cfg_mode(0) AND adr(3) AND NOT cctl AND 
	reset_n_sync AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (use_cart_logic/cfg_bank(17) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$36 AND use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(2) AND use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_bank(17) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (use_cart_logic/cfg_mode(4) AND 
	NOT use_cart_logic/cfg_mode(0) AND use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_bank(17) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_bank(17) AND reset_n_sync AND NOT $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND NOT use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(0) AND use_cart_logic/cfg_mode(1) AND NOT rw AND data(4).PIN AND 
	NOT cctl AND reset_n_sync AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (use_cart_logic/cfg_bank(17) AND $OpTx$FX_SC$112)
	OR (data(4).PIN AND $OpTx$FX_DC$84)
	OR (use_cart_logic/cfg_bank(17) AND 
	use_cart_logic/N26/use_cart_logic/N26_D2 AND $OpTx$FX_DC$35)
	OR (use_cart_logic/cfg_mode(2) AND NOT rw AND NOT cctl AND 
	data(3).PIN AND reset_n_sync AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2)
	OR (NOT rw AND NOT cctl AND data(3).PIN AND reset_n_sync AND 
	NOT $OpTx$FX_DC$36 AND 
	use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2));

FDCPE_use_cart_logic/cfg_bank18: FDCPE port map (use_cart_logic/cfg_bank(18),use_cart_logic/cfg_bank_D(18),NOT phi2short,'0','0');
use_cart_logic/cfg_bank_D(18) <= ((use_cart_logic/cfg_mode(0) AND adr(5) AND NOT cctl AND 
	reset_n_sync AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT use_cart_logic/cfg_mode(0) AND NOT cctl AND adr(4) AND 
	reset_n_sync AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(0) AND NOT rw AND data(4).PIN AND NOT cctl AND reset_n_sync AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2)
	OR (use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(1) AND NOT rw AND data(4).PIN AND NOT cctl AND reset_n_sync AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2)
	OR (NOT use_cart_logic/cfg_mode(0) AND 
	NOT use_cart_logic/cfg_mode(1) AND use_cart_logic/cfg_bank(18) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (NOT use_cart_logic/cfg_mode(0) AND 
	NOT use_cart_logic/cfg_mode(1) AND NOT rw AND NOT cctl AND data(5).PIN AND reset_n_sync AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (use_cart_logic/cfg_bank(18) AND $OpTx$FX_SC$112)
	OR (data(5).PIN AND $OpTx$FX_DC$84)
	OR (use_cart_logic/cfg_bank(18) AND 
	use_cart_logic/N26/use_cart_logic/N26_D2 AND $OpTx$FX_DC$35)
	OR (use_cart_logic/cfg_bank(18) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2 AND NOT $OpTx$FX_DC$71)
	OR (NOT rw AND data(4).PIN AND NOT cctl AND reset_n_sync AND 
	NOT $OpTx$FX_DC$36 AND 
	use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2));

FDCPE_use_cart_logic/cfg_bank19: FDCPE port map (use_cart_logic/cfg_bank(19),use_cart_logic/cfg_bank_D(19),NOT phi2short,'0','0');
use_cart_logic/cfg_bank_D(19) <= ((use_cart_logic/cfg_mode(4) AND 
	NOT use_cart_logic/cfg_mode(0) AND use_cart_logic/cfg_bank(19) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_mode(0) AND adr(6) AND NOT cctl AND 
	reset_n_sync AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT use_cart_logic/cfg_mode(0) AND adr(5) AND NOT cctl AND 
	reset_n_sync AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT rw AND data(6).PIN AND NOT cctl AND reset_n_sync AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT use_cart_logic/cfg_mode(1) AND NOT rw AND data(6).PIN AND 
	NOT cctl AND reset_n_sync AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(1) AND NOT rw AND NOT cctl AND data(5).PIN AND reset_n_sync AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2)
	OR (NOT use_cart_logic/cfg_mode(2) AND NOT rw AND data(6).PIN AND 
	NOT cctl AND reset_n_sync AND NOT $OpTx$FX_DC$36 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (NOT rw AND data(6).PIN AND NOT cctl AND reset_n_sync AND 
	NOT $OpTx$FX_DC$36 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	NOT use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(0) AND NOT use_cart_logic/cfg_mode(1) AND NOT rw AND data(6).PIN AND 
	NOT cctl AND reset_n_sync AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (use_cart_logic/cfg_bank(19) AND $OpTx$FX_SC$112)
	OR (use_cart_logic/cfg_bank(19) AND rw AND reset_n_sync AND 
	use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (use_cart_logic/cfg_bank(19) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (use_cart_logic/cfg_bank(19) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND NOT $OpTx$FX_DC$71)
	OR (NOT use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_bank(19) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND 
	use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2));

FDCPE_use_cart_logic/cfg_bank20: FDCPE port map (use_cart_logic/cfg_bank(20),use_cart_logic/cfg_bank_D(20),NOT phi2short,'0','0');
use_cart_logic/cfg_bank_D(20) <= ((NOT use_cart_logic/cfg_mode(5) AND 
	use_cart_logic/cfg_bank(20) AND reset_n_sync AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (NOT use_cart_logic/cfg_mode(0) AND adr(6) AND NOT cctl AND 
	reset_n_sync AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT rw AND data(6).PIN AND NOT cctl AND reset_n_sync AND 
	NOT $OpTx$FX_DC$36 AND $OpTx$FX_DC$124)
	OR (NOT rw AND NOT cctl AND data(7).PIN AND reset_n_sync AND 
	NOT $OpTx$FX_DC$36 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND NOT $OpTx$FX_DC$124)
	OR (NOT use_cart_logic/cfg_mode(4) AND NOT rw AND NOT cctl AND 
	data(7).PIN AND reset_n_sync AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT use_cart_logic/cfg_mode(5) AND NOT rw AND NOT cctl AND 
	data(7).PIN AND reset_n_sync AND $OpTx$FX_DC$36 AND 
	use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2)
	OR (use_cart_logic/cfg_bank(20) AND $OpTx$FX_SC$112)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_bank(20) AND rw AND reset_n_sync AND 
	use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_bank(20) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND use_cart_logic/N26/use_cart_logic/N26_D2)
	OR (NOT use_cart_logic/cfg_mode(5) AND 
	use_cart_logic/cfg_bank(20) AND rw AND reset_n_sync AND $OpTx$FX_DC$36)
	OR (use_cart_logic/cfg_bank(20) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND NOT $OpTx$FX_DC$124));

FDCPE_use_cart_logic/cfg_bank21: FDCPE port map (use_cart_logic/cfg_bank(21),use_cart_logic/cfg_bank_D(21),NOT phi2short,'0','0');
use_cart_logic/cfg_bank_D(21) <= ((use_cart_logic/cfg_bank(21) AND adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(21) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND NOT adr(1) AND NOT adr(2) AND adr(0) AND NOT cctl AND 
	data(0).PIN AND reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT cctl AND data(0).PIN AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT $OpTx$FX_DC$6)
	OR (use_cart_logic/cfg_bank(21) AND adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(21) AND NOT adr(0) AND 
	reset_n_sync));

FDCPE_use_cart_logic/cfg_bank22: FDCPE port map (use_cart_logic/cfg_bank(22),use_cart_logic/cfg_bank_D(22),NOT phi2short,'0','0');
use_cart_logic/cfg_bank_D(22) <= ((NOT adr(3) AND NOT adr(1) AND NOT adr(2) AND adr(0) AND NOT cctl AND 
	data(1).PIN AND reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT cctl AND data(1).PIN AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT $OpTx$FX_DC$6)
	OR (use_cart_logic/cfg_bank(22) AND adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(22) AND adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(22) AND NOT adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(22) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6));

FDCPE_use_cart_logic/cfg_bank23: FDCPE port map (use_cart_logic/cfg_bank(23),use_cart_logic/cfg_bank_D(23),NOT phi2short,'0','0');
use_cart_logic/cfg_bank_D(23) <= ((NOT adr(3) AND NOT adr(1) AND NOT adr(2) AND adr(0) AND 
	data(2).PIN AND NOT cctl AND reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT adr(3) AND NOT adr(2) AND adr(0) AND data(2).PIN AND NOT cctl AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT $OpTx$FX_DC$6)
	OR (use_cart_logic/cfg_bank(23) AND adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(23) AND adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(23) AND NOT adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(23) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6));

FDCPE_use_cart_logic/cfg_bank24: FDCPE port map (use_cart_logic/cfg_bank(24),use_cart_logic/cfg_bank_D(24),NOT phi2short,'0','0');
use_cart_logic/cfg_bank_D(24) <= ((use_cart_logic/cfg_bank(24) AND adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(24) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND NOT adr(1) AND NOT adr(2) AND adr(0) AND NOT cctl AND 
	data(3).PIN AND reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT cctl AND data(3).PIN AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT $OpTx$FX_DC$6)
	OR (use_cart_logic/cfg_bank(24) AND adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(24) AND NOT adr(0) AND 
	reset_n_sync));

FDCPE_use_cart_logic/cfg_bank25: FDCPE port map (use_cart_logic/cfg_bank(25),use_cart_logic/cfg_bank_D(25),NOT phi2short,'0','0');
use_cart_logic/cfg_bank_D(25) <= ((use_cart_logic/cfg_bank(25) AND adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(25) AND adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(25) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND NOT adr(1) AND NOT adr(2) AND data(4).PIN AND 
	adr(0) AND NOT cctl AND reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT adr(3) AND NOT adr(2) AND data(4).PIN AND adr(0) AND NOT cctl AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT $OpTx$FX_DC$6)
	OR (use_cart_logic/cfg_bank(25) AND NOT adr(0) AND 
	reset_n_sync));

FDCPE_use_cart_logic/cfg_bank26: FDCPE port map (use_cart_logic/cfg_bank(26),use_cart_logic/cfg_bank_D(26),NOT phi2short,'0','0');
use_cart_logic/cfg_bank_D(26) <= ((NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT cctl AND data(5).PIN AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT $OpTx$FX_DC$6)
	OR (use_cart_logic/cfg_bank(26) AND adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(26) AND adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(26) AND NOT adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_bank(26) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND NOT adr(1) AND NOT adr(2) AND adr(0) AND NOT cctl AND 
	data(5).PIN AND reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2));


use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2 <= (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(2) AND use_cart_logic/cfg_mode(3) AND 
	NOT use_cart_logic/cfg_mode(0) AND NOT use_cart_logic/cfg_mode(1) AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2);


use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 <= (NOT adr(6) AND NOT adr(3) AND adr(7) AND adr(5) AND NOT adr(1) AND 
	NOT adr(2) AND NOT adr(0) AND NOT adr(4));


use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2 <= (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(5) AND use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(3) AND NOT use_cart_logic/cfg_mode(0) AND 
	NOT use_cart_logic/cfg_mode(1) AND NOT adr(7) AND $OpTx$FX_DC$22);

FDCPE_use_cart_logic/cfg_enable: FDCPE port map (use_cart_logic/cfg_enable,use_cart_logic/cfg_enable_D,NOT phi2short,'0','0');
use_cart_logic/cfg_enable_D <= ((NOT reset_n_sync)
	OR (NOT use_cart_logic/cfg_mode(1) AND 
	use_cart_logic/cfg_enable AND rw AND use_cart_logic/N145/use_cart_logic/N145_D2)
	OR (NOT rw AND NOT cctl AND NOT data(7).PIN AND 
	use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2)
	OR (NOT use_cart_logic/cfg_mode(5) AND 
	use_cart_logic/cfg_enable AND rw AND NOT $OpTx$INV$2 AND NOT $OpTx$FX_DC$56)
	OR (NOT use_cart_logic/cfg_mode(3) AND 
	NOT use_cart_logic/cfg_mode(1) AND NOT rw AND NOT cctl AND NOT $OpTx$INV$3)
	OR (NOT rw AND NOT cctl AND NOT $OpTx$FX_DC$36 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT $OpTx$INV$3)
	OR (use_cart_logic/cfg_mode(4) AND 
	NOT use_cart_logic/cfg_mode(3) AND NOT rw AND NOT cctl AND NOT $OpTx$INV$3)
	OR (use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(3) AND NOT rw AND NOT cctl AND NOT $OpTx$INV$3)
	OR (use_cart_logic/cfg_mode(5) AND 
	use_cart_logic/cfg_mode(3) AND NOT rw AND NOT cctl AND NOT data(7).PIN AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT use_cart_logic/cfg_mode(5) AND NOT rw AND NOT cctl AND 
	NOT $OpTx$FX_DC$36 AND NOT $OpTx$INV$3 AND 
	NOT use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2)
	OR (NOT use_cart_logic/cfg_mode(5) AND NOT rw AND NOT cctl AND 
	use_cart_logic/N145/use_cart_logic/N145_D2 AND NOT $OpTx$INV$2 AND NOT $OpTx$INV$3 AND NOT $OpTx$FX_DC$56)
	OR (use_cart_logic/cfg_enable AND cctl)
	OR (use_cart_logic/cfg_enable AND rw AND NOT $OpTx$FX_DC$36)
	OR (NOT cctl AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N145/use_cart_logic/N145_D2 AND NOT $OpTx$FX_DC$137)
	OR (NOT cctl AND use_cart_logic/N145/use_cart_logic/N145_D2 AND 
	NOT $OpTx$FX_DC$42 AND $OpTx$FX_DC$158));

FDCPE_use_cart_logic/cfg_enable2: FDCPE port map (use_cart_logic/cfg_enable2,use_cart_logic/cfg_enable2_D,NOT phi2short,'0','0');
use_cart_logic/cfg_enable2_D <= ((use_cart_logic/cfg_enable2 AND adr(1) AND 
	reset_n_sync)
	OR (adr(1) AND NOT adr(2) AND adr(0) AND reset_n_sync AND 
	$OpTx$FX_DC$6)
	OR (NOT adr(1) AND adr(2) AND data(0).PIN AND reset_n_sync AND 
	$OpTx$FX_DC$6)
	OR (use_cart_logic/cfg_enable2 AND NOT adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_enable2 AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(1) AND NOT adr(0) AND reset_n_sync AND 
	NOT use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 AND $OpTx$FX_DC$6));

FDCPE_use_cart_logic/cfg_mode0: FDCPE port map (use_cart_logic/cfg_mode(0),use_cart_logic/cfg_mode_D(0),NOT phi2short,'0','0');
use_cart_logic/cfg_mode_D(0) <= ((NOT reset_n_sync)
	OR (use_cart_logic/cfg_mode(0) AND NOT adr(1))
	OR (use_cart_logic/cfg_mode(0) AND NOT adr(2))
	OR (use_cart_logic/cfg_mode(0) AND adr(0))
	OR (use_cart_logic/cfg_mode(0) AND NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND adr(1) AND adr(2) AND NOT adr(0) AND NOT cctl AND 
	data(0).PIN AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2));

FDCPE_use_cart_logic/cfg_mode1: FDCPE port map (use_cart_logic/cfg_mode(1),use_cart_logic/cfg_mode_D(1),NOT phi2short,'0','0');
use_cart_logic/cfg_mode_D(1) <= ((use_cart_logic/cfg_mode(1) AND adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_mode(1) AND NOT adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_mode(1) AND NOT adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_mode(1) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND adr(1) AND adr(2) AND NOT adr(0) AND NOT cctl AND 
	data(1).PIN AND reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2));

FDCPE_use_cart_logic/cfg_mode2: FDCPE port map (use_cart_logic/cfg_mode(2),use_cart_logic/cfg_mode_D(2),NOT phi2short,'0','0');
use_cart_logic/cfg_mode_D(2) <= ((use_cart_logic/cfg_mode(2) AND NOT adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_mode(2) AND adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_mode(2) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND adr(1) AND adr(2) AND NOT adr(0) AND 
	data(2).PIN AND NOT cctl AND reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (use_cart_logic/cfg_mode(2) AND NOT adr(1) AND 
	reset_n_sync));

FDCPE_use_cart_logic/cfg_mode3: FDCPE port map (use_cart_logic/cfg_mode(3),use_cart_logic/cfg_mode_D(3),NOT phi2short,'0','0');
use_cart_logic/cfg_mode_D(3) <= ((use_cart_logic/cfg_mode(3) AND NOT adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_mode(3) AND adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_mode(3) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND adr(1) AND adr(2) AND NOT adr(0) AND NOT cctl AND 
	data(3).PIN AND reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (use_cart_logic/cfg_mode(3) AND NOT adr(1) AND 
	reset_n_sync));

FDCPE_use_cart_logic/cfg_mode4: FDCPE port map (use_cart_logic/cfg_mode(4),use_cart_logic/cfg_mode_D(4),NOT phi2short,'0','0');
use_cart_logic/cfg_mode_D(4) <= ((use_cart_logic/cfg_mode(4) AND adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_mode(4) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND adr(1) AND adr(2) AND data(4).PIN AND 
	NOT adr(0) AND NOT cctl AND reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (use_cart_logic/cfg_mode(4) AND NOT adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_mode(4) AND NOT adr(2) AND 
	reset_n_sync));

FDCPE_use_cart_logic/cfg_mode5: FDCPE port map (use_cart_logic/cfg_mode(5),use_cart_logic/cfg_mode_D(5),NOT phi2short,'0','0');
use_cart_logic/cfg_mode_D(5) <= ((use_cart_logic/cfg_mode(5) AND adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_mode(5) AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND adr(1) AND adr(2) AND NOT adr(0) AND NOT cctl AND 
	data(5).PIN AND reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (use_cart_logic/cfg_mode(5) AND NOT adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_mode(5) AND NOT adr(2) AND 
	reset_n_sync));

FDCPE_use_cart_logic/cfg_source_ram: FDCPE port map (use_cart_logic/cfg_source_ram,use_cart_logic/cfg_source_ram_D,NOT phi2short,'0','0');
use_cart_logic/cfg_source_ram_D <= ((use_cart_logic/cfg_source_ram AND NOT adr(2) AND 
	reset_n_sync)
	OR (NOT adr(3) AND adr(1) AND adr(2) AND adr(0) AND NOT cctl AND 
	data(1).PIN AND reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT adr(3) AND adr(1) AND adr(0) AND NOT cctl AND data(1).PIN AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT $OpTx$FX_DC$6)
	OR (use_cart_logic/cfg_source_ram AND NOT adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_source_ram AND NOT adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_source_ram AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6));

FDCPE_use_cart_logic/cfg_source_ram2: FDCPE port map (use_cart_logic/cfg_source_ram2,use_cart_logic/cfg_source_ram2_D,NOT phi2short,'0','0');
use_cart_logic/cfg_source_ram2_D <= ((NOT adr(3) AND adr(1) AND adr(2) AND adr(0) AND NOT cctl AND 
	data(3).PIN AND reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT adr(3) AND adr(1) AND adr(0) AND NOT cctl AND data(3).PIN AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT $OpTx$FX_DC$6)
	OR (use_cart_logic/cfg_source_ram2 AND NOT adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_source_ram2 AND NOT adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_source_ram2 AND NOT adr(0) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_source_ram2 AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6));

FDCPE_use_cart_logic/cfg_write_enable2: FDCPE port map (use_cart_logic/cfg_write_enable2,use_cart_logic/cfg_write_enable2_D,NOT phi2short,'0','0');
use_cart_logic/cfg_write_enable2_D <= ((use_cart_logic/cfg_write_enable2 AND NOT adr(2) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_write_enable2 AND reset_n_sync AND 
	NOT $OpTx$FX_DC$6)
	OR (NOT adr(3) AND adr(1) AND adr(2) AND adr(0) AND 
	data(2).PIN AND NOT cctl AND reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2)
	OR (NOT adr(3) AND adr(1) AND adr(0) AND data(2).PIN AND NOT cctl AND 
	reset_n_sync AND NOT data_or0000/data_or0000_D2 AND 
	use_cart_logic/N230/use_cart_logic/N230_D2 AND NOT $OpTx$FX_DC$6)
	OR (use_cart_logic/cfg_write_enable2 AND NOT adr(1) AND 
	reset_n_sync)
	OR (use_cart_logic/cfg_write_enable2 AND NOT adr(0) AND 
	reset_n_sync));

FTCPE_use_cart_logic/oss_bank0: FTCPE port map (use_cart_logic/oss_bank(0),use_cart_logic/oss_bank_T(0),NOT phi2short,'0','0');
use_cart_logic/oss_bank_T(0) <= ((use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(3) AND NOT use_cart_logic/cfg_mode(0) AND NOT adr(7) AND 
	use_cart_logic/oss_bank(0) AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND $OpTx$FX_DC$22)
	OR (use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(0) AND NOT adr(7) AND use_cart_logic/oss_bank(0) AND 
	$OpTx$FX_DC$36 AND NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/N26/use_cart_logic/N26_D2 AND $OpTx$FX_DC$22)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(2) AND NOT use_cart_logic/cfg_mode(3) AND NOT adr(3) AND NOT adr(7) AND 
	NOT use_cart_logic/oss_bank(0) AND reset_n_sync AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND use_cart_logic/N26/use_cart_logic/N26_D2 AND 
	$OpTx$FX_DC$22)
	OR (use_cart_logic/oss_bank(0) AND NOT reset_n_sync)
	OR (use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(2) AND NOT use_cart_logic/cfg_mode(0) AND NOT adr(7) AND 
	use_cart_logic/oss_bank(0) AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND $OpTx$FX_DC$22)
	OR (use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(0) AND adr(3) AND NOT adr(7) AND use_cart_logic/oss_bank(0) AND 
	$OpTx$FX_DC$36 AND NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	$OpTx$FX_DC$22));

FTCPE_use_cart_logic/oss_bank1: FTCPE port map (use_cart_logic/oss_bank(1),use_cart_logic/oss_bank_T(1),NOT phi2short,'0','0');
use_cart_logic/oss_bank_T(1) <= ((use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(2) AND NOT use_cart_logic/cfg_mode(0) AND NOT adr(7) AND 
	use_cart_logic/oss_bank(1) AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND $OpTx$FX_DC$22)
	OR (use_cart_logic/cfg_mode(2) AND 
	use_cart_logic/cfg_mode(3) AND NOT use_cart_logic/cfg_mode(0) AND NOT adr(7) AND 
	use_cart_logic/oss_bank(1) AND $OpTx$FX_DC$36 AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND $OpTx$FX_DC$22)
	OR (use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(0) AND NOT adr(7) AND use_cart_logic/oss_bank(1) AND NOT adr(0) AND 
	$OpTx$FX_DC$36 AND NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	$OpTx$FX_DC$22)
	OR (use_cart_logic/cfg_mode(2) AND 
	NOT use_cart_logic/cfg_mode(0) AND NOT adr(7) AND use_cart_logic/oss_bank(1) AND 
	$OpTx$FX_DC$36 AND NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND 
	NOT use_cart_logic/N26/use_cart_logic/N26_D2 AND $OpTx$FX_DC$22)
	OR (NOT use_cart_logic/cfg_mode(4) AND 
	use_cart_logic/cfg_mode(2) AND NOT use_cart_logic/cfg_mode(3) AND NOT adr(7) AND 
	NOT use_cart_logic/oss_bank(1) AND adr(0) AND reset_n_sync AND 
	NOT use_cart_logic/N230/use_cart_logic/N230_D2 AND use_cart_logic/N26/use_cart_logic/N26_D2 AND 
	$OpTx$FX_DC$22)
	OR (use_cart_logic/oss_bank(1) AND NOT reset_n_sync));

FTCPE_use_cart_logic/sic_8xxx_enable: FTCPE port map (use_cart_logic/sic_8xxx_enable,use_cart_logic/sic_8xxx_enable_T,NOT phi2short,'0','0');
use_cart_logic/sic_8xxx_enable_T <= ((use_cart_logic/sic_8xxx_enable AND NOT reset_n_sync)
	OR (use_cart_logic/sic_8xxx_enable AND NOT rw AND NOT cctl AND 
	NOT data(5).PIN AND 
	use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (NOT use_cart_logic/sic_8xxx_enable AND NOT rw AND NOT cctl AND 
	data(5).PIN AND reset_n_sync AND 
	use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2));

FTCPE_use_cart_logic/sic_axxx_enable: FTCPE port map (use_cart_logic/sic_axxx_enable,use_cart_logic/sic_axxx_enable_T,NOT phi2short,'0','0');
use_cart_logic/sic_axxx_enable_T <= ((NOT use_cart_logic/sic_axxx_enable AND NOT reset_n_sync)
	OR (NOT use_cart_logic/sic_axxx_enable AND NOT rw AND 
	NOT data(6).PIN AND NOT cctl AND 
	use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2)
	OR (use_cart_logic/sic_axxx_enable AND NOT rw AND 
	data(6).PIN AND NOT cctl AND reset_n_sync AND 
	use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95144XL-10-TQ100


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 |   99  97  95  93  91  89  87  85  83  81  79  77    |
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 | 13              XC95144XL-10-TQ100              63  | 
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 |   27  29  31  33  35  37  39  41  43  45  47  49    |
  \26  28  30  32  34  36  38  40  42  44  46  48  50  /
   --------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 data<4>                          51 VCC                           
  2 PGND                             52 ram_rom_adr<2>                
  3 s4                               53 ram_rom_adr<3>                
  4 s5                               54 ram_rom_adr<4>                
  5 VCC                              55 ram_rom_adr<5>                
  6 data<5>                          56 ram_rom_adr<6>                
  7 PGND                             57 VCC                           
  8 data<2>                          58 ram_rom_adr<7>                
  9 data<1>                          59 ram_rom_adr<8>                
 10 data<3>                          60 ram_rom_adr<18>               
 11 data<0>                          61 ram_rom_adr<19>               
 12 data<7>                          62 GND                           
 13 data<6>                          63 ram_rom_adr<22>               
 14 adr<11>                          64 ram_rom_adr<21>               
 15 adr<10>                          65 ram_rom_adr<20>               
 16 eeprom_cs                        66 ram_rom_adr<9>                
 17 eeprom_so                        67 ram_rom_adr<10>               
 18 eeprom_sck                       68 ram_rom_adr<11>               
 19 PGND                             69 GND                           
 20 eeprom_si                        70 ram_rom_adr<12>               
 21 GND                              71 ram_rom_adr<13>               
 22 phi2                             72 ram_rom_adr<14>               
 23 phi2short                        73 mod_en                        
 24 ram_rom_adr<26>                  74 ram_rom_adr<15>               
 25 ram_rom_adr<0>                   75 GND                           
 26 VCC                              76 ram_rom_adr<16>               
 27 cctl                             77 ram_rom_adr<23>               
 28 ram_rom_adr<17>                  78 ram_rom_adr<24>               
 29 ram_rom_adr<25>                  79 rd5                           
 30 rom_reset                        80 PGND                          
 31 GND                              81 rd4                           
 32 ram_rom_data<7>                  82 reset_n                       
 33 ram_rom_data<6>                  83 TDO                           
 34 PGND                             84 GND                           
 35 ram_rom_data<5>                  85 ram_ce                        
 36 ram_rom_data<4>                  86 adr<3>                        
 37 ram_rom_data<3>                  87 adr<4>                        
 38 VCC                              88 VCC                           
 39 ram_rom_data<2>                  89 adr<2>                        
 40 ram_rom_data<1>                  90 adr<5>                        
 41 ram_rom_data<0>                  91 adr<1>                        
 42 ram_rom_oe                       92 adr<6>                        
 43 ram_rom_adr<1>                   93 adr<0>                        
 44 GND                              94 adr<7>                        
 45 TDI                              95 adr<8>                        
 46 PGND                             96 adr<9>                        
 47 TMS                              97 adr<12>                       
 48 TCK                              98 VCC                           
 49 rom_ce                           99 rw                            
 50 ram_rom_we                      100 GND                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95144xl-10-TQ100
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Power Mode                                  : LOW
Ground on Unused IOs                        : ON
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 30
Pterm Limit                                 : 15