Timing Report

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Design Name TheCart
Device, Speed (SpeedFile Version) XC95144XL, -10 (3.0)
Date Created Sun Oct 27 13:13:43 2013
Created By Timing Report Generator: version M.81d
Copyright Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 70.300 ns.
Max. Clock Frequency (fSYSTEM) 14.225 MHz.
Limited by Cycle Time for phi2short
Clock to Setup (tCYC) 70.300 ns.
Pad to Pad Delay (tPD) 51.600 ns.
Setup to Clock at the Pad (tSU) 67.800 ns.
Clock Pad to Output Pad Delay (tCO) 67.300 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 70.3 171 171
AUTO_TS_P2P 0.0 67.3 198 198
AUTO_TS_P2F 0.0 69.6 512 512
AUTO_TS_F2P 0.0 65.5 306 306


Constraint: TS1000

Description: PERIOD:PERIOD_phi2short:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
use_cart_logic/cfg_mode<0>.Q to use_cart_logic/cfg_bank<13>.D 0.000 70.300 -70.300
use_cart_logic/cfg_mode<1>.Q to use_cart_logic/cfg_bank<13>.D 0.000 70.300 -70.300
use_cart_logic/cfg_mode<2>.Q to use_cart_logic/cfg_bank<13>.D 0.000 70.300 -70.300


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
phi2short to data<0> 0.000 67.300 -67.300
phi2short to data<1> 0.000 67.300 -67.300
phi2short to data<2> 0.000 67.300 -67.300


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
adr<4> to use_cart_logic/cfg_bank<13>.D 0.000 69.600 -69.600
adr<4> to use_cart_logic/cfg_bank<16>.D 0.000 69.600 -69.600
adr<5> to use_cart_logic/cfg_bank<13>.D 0.000 69.600 -69.600


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
use_cart_logic/cfg_mode<0>.Q to data<0> 0.000 65.500 -65.500
use_cart_logic/cfg_mode<0>.Q to data<1> 0.000 65.500 -65.500
use_cart_logic/cfg_mode<0>.Q to data<2> 0.000 65.500 -65.500



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
phi2short 14.225 Limited by Cycle Time for phi2short

Setup/Hold Times for Clocks

Setup/Hold Times for Clock phi2short
Source Pad Setup to clk (edge) Hold to clk (edge)
adr<0> 65.800 0.000
adr<1> 65.800 0.000
adr<2> 65.800 0.000
adr<3> 65.800 0.000
adr<4> 67.800 0.000
adr<5> 67.800 0.000
adr<6> 67.800 0.000
adr<7> 67.800 0.000
cctl 67.800 0.000
data<0> 52.600 0.000
data<1> 13.400 0.000
data<2> 26.200 0.000
data<3> 26.200 0.000
data<4> 13.000 0.000
data<5> 13.000 0.000
data<6> 13.000 0.000
data<7> 13.000 0.000
reset_n 13.000 0.000
rw 52.600 0.000


Clock to Pad Timing

Clock phi2short to Pad
Destination Pad Clock (edge) to Pad
data<0> 67.300
data<1> 67.300
data<2> 67.300
data<3> 67.300
data<4> 67.300
data<5> 67.300
data<6> 67.300
data<7> 67.300
ram_ce 64.100
ram_rom_adr<13> 64.100
ram_rom_adr<15> 64.100
rom_ce 64.100
ram_rom_adr<12> 50.900
ram_rom_adr<19> 50.900
ram_rom_adr<22> 50.900
ram_rom_adr<24> 50.900
ram_rom_adr<26> 50.900
ram_rom_adr<14> 49.900
ram_rom_adr<16> 49.900
ram_rom_adr<17> 49.900
ram_rom_adr<18> 49.900
ram_rom_adr<20> 49.900
ram_rom_adr<21> 49.900
ram_rom_adr<23> 49.900
ram_rom_adr<25> 49.900
rd5 49.900
rd4 24.500
eeprom_cs 10.300
eeprom_sck 10.300
eeprom_si 10.300
mod_en 10.300
rom_reset 10.300


Clock to Setup Times for Clocks

Clock to Setup for clock phi2short
Source Destination Delay
use_cart_logic/cfg_mode<0>.Q use_cart_logic/cfg_bank<13>.D 70.300
use_cart_logic/cfg_mode<1>.Q use_cart_logic/cfg_bank<13>.D 70.300
use_cart_logic/cfg_mode<2>.Q use_cart_logic/cfg_bank<13>.D 70.300
use_cart_logic/cfg_mode<3>.Q use_cart_logic/cfg_bank<13>.D 70.300
use_cart_logic/cfg_mode<5>.Q use_cart_logic/cfg_bank<13>.D 70.300
use_cart_logic/cfg_mode<0>.Q use_cart_logic/cfg_bank<14>.D 69.300
use_cart_logic/cfg_mode<0>.Q use_cart_logic/cfg_bank<15>.D 69.300
use_cart_logic/cfg_mode<1>.Q use_cart_logic/cfg_bank<14>.D 69.300
use_cart_logic/cfg_mode<1>.Q use_cart_logic/cfg_bank<15>.D 69.300
use_cart_logic/cfg_mode<2>.Q use_cart_logic/cfg_bank<14>.D 69.300
use_cart_logic/cfg_mode<2>.Q use_cart_logic/cfg_bank<15>.D 69.300
use_cart_logic/cfg_mode<3>.Q use_cart_logic/cfg_bank<14>.D 69.300
use_cart_logic/cfg_mode<3>.Q use_cart_logic/cfg_bank<15>.D 69.300
use_cart_logic/cfg_mode<5>.Q use_cart_logic/cfg_bank<14>.D 69.300
use_cart_logic/cfg_mode<5>.Q use_cart_logic/cfg_bank<15>.D 69.300
use_cart_logic/cfg_mode<0>.Q use_cart_logic/cfg_enable.D 57.100
use_cart_logic/cfg_mode<1>.Q use_cart_logic/cfg_enable.D 57.100
use_cart_logic/cfg_mode<2>.Q use_cart_logic/cfg_enable.D 57.100
use_cart_logic/cfg_mode<3>.Q use_cart_logic/cfg_bank<16>.D 57.100
use_cart_logic/cfg_mode<3>.Q use_cart_logic/cfg_enable.D 57.100
use_cart_logic/cfg_mode<4>.Q use_cart_logic/cfg_bank<13>.D 57.100
use_cart_logic/cfg_mode<4>.Q use_cart_logic/cfg_bank<16>.D 57.100
use_cart_logic/cfg_mode<5>.Q use_cart_logic/cfg_bank<16>.D 57.100
use_cart_logic/cfg_mode<5>.Q use_cart_logic/cfg_enable.D 57.100
use_cart_logic/cfg_bank<13>.Q use_cart_logic/cfg_bank<13>.D 56.100
use_cart_logic/cfg_mode<0>.Q use_cart_logic/cfg_bank<16>.D 56.100
use_cart_logic/cfg_mode<0>.Q use_cart_logic/cfg_bank<17>.D 56.100
use_cart_logic/cfg_mode<0>.Q use_cart_logic/cfg_bank<18>.D 56.100
use_cart_logic/cfg_mode<1>.Q use_cart_logic/cfg_bank<16>.D 56.100
use_cart_logic/cfg_mode<1>.Q use_cart_logic/cfg_bank<17>.D 56.100
use_cart_logic/cfg_mode<1>.Q use_cart_logic/cfg_bank<18>.D 56.100
use_cart_logic/cfg_mode<2>.Q use_cart_logic/cfg_bank<16>.D 56.100
use_cart_logic/cfg_mode<2>.Q use_cart_logic/cfg_bank<17>.D 56.100
use_cart_logic/cfg_mode<2>.Q use_cart_logic/cfg_bank<18>.D 56.100
use_cart_logic/cfg_mode<3>.Q use_cart_logic/cfg_bank<17>.D 56.100
use_cart_logic/cfg_mode<3>.Q use_cart_logic/cfg_bank<18>.D 56.100
use_cart_logic/cfg_mode<4>.Q use_cart_logic/cfg_bank<14>.D 56.100
use_cart_logic/cfg_mode<4>.Q use_cart_logic/cfg_bank<15>.D 56.100
use_cart_logic/cfg_mode<5>.Q use_cart_logic/cfg_bank<17>.D 56.100
use_cart_logic/cfg_mode<5>.Q use_cart_logic/cfg_bank<18>.D 56.100
use_cart_logic/cfg_mode<0>.Q use_cart_logic/cfg_bank<19>.D 55.100
use_cart_logic/cfg_mode<0>.Q use_cart_logic/cfg_bank<20>.D 55.100
use_cart_logic/cfg_mode<1>.Q use_cart_logic/cfg_bank<19>.D 55.100
use_cart_logic/cfg_mode<1>.Q use_cart_logic/cfg_bank<20>.D 55.100
use_cart_logic/cfg_mode<2>.Q use_cart_logic/cfg_bank<19>.D 55.100
use_cart_logic/cfg_mode<2>.Q use_cart_logic/cfg_bank<20>.D 55.100
use_cart_logic/cfg_mode<3>.Q use_cart_logic/cfg_bank<19>.D 55.100
use_cart_logic/cfg_mode<3>.Q use_cart_logic/cfg_bank<20>.D 55.100
use_cart_logic/cfg_mode<5>.Q use_cart_logic/cfg_bank<19>.D 55.100
use_cart_logic/cfg_mode<5>.Q use_cart_logic/cfg_bank<20>.D 55.100
use_cart_logic/cfg_mode<4>.Q use_cart_logic/cfg_enable.D 43.900
reset_n_sync.Q use_cart_logic/cfg_bank<13>.D 42.900
use_cart_logic/cfg_enable.Q use_cart_logic/cfg_enable.D 42.900
use_cart_logic/cfg_mode<0>.Q use_cart_logic/oss_bank<0>.D 42.900
use_cart_logic/cfg_mode<0>.Q use_cart_logic/oss_bank<1>.D 42.900
use_cart_logic/cfg_mode<1>.Q use_cart_logic/oss_bank<0>.D 42.900
use_cart_logic/cfg_mode<1>.Q use_cart_logic/oss_bank<1>.D 42.900
use_cart_logic/cfg_mode<2>.Q use_cart_logic/oss_bank<0>.D 42.900
use_cart_logic/cfg_mode<2>.Q use_cart_logic/oss_bank<1>.D 42.900
use_cart_logic/cfg_mode<3>.Q use_cart_logic/oss_bank<0>.D 42.900
use_cart_logic/cfg_mode<3>.Q use_cart_logic/oss_bank<1>.D 42.900
use_cart_logic/cfg_mode<4>.Q use_cart_logic/cfg_bank<17>.D 42.900
use_cart_logic/cfg_mode<4>.Q use_cart_logic/cfg_bank<18>.D 42.900
use_cart_logic/cfg_mode<4>.Q use_cart_logic/cfg_bank<20>.D 42.900
use_cart_logic/cfg_mode<5>.Q use_cart_logic/oss_bank<0>.D 42.900
use_cart_logic/cfg_mode<5>.Q use_cart_logic/oss_bank<1>.D 42.900
use_cart_logic/cfg_mode<4>.Q use_cart_logic/cfg_bank<19>.D 41.900
reset_n_sync.Q use_cart_logic/cfg_bank<16>.D 29.700
reset_n_sync.Q use_cart_logic/cfg_bank<17>.D 29.700
reset_n_sync.Q use_cart_logic/cfg_bank<18>.D 29.700
use_cart_logic/cfg_bank<16>.Q use_cart_logic/cfg_bank<16>.D 29.700
use_cart_logic/cfg_mode<4>.Q use_cart_logic/oss_bank<0>.D 29.700
use_cart_logic/cfg_mode<4>.Q use_cart_logic/oss_bank<1>.D 29.700
reset_n_sync.Q use_cart_logic/cfg_bank<14>.D 28.700
reset_n_sync.Q use_cart_logic/cfg_bank<15>.D 28.700
reset_n_sync.Q use_cart_logic/cfg_bank<19>.D 28.700
reset_n_sync.Q use_cart_logic/cfg_bank<20>.D 28.700
use_cart_logic/cfg_mode<0>.Q use_cart_logic/sic_8xxx_enable.D 28.700
use_cart_logic/cfg_mode<0>.Q use_cart_logic/sic_axxx_enable.D 28.700
use_cart_logic/cfg_mode<1>.Q use_cart_logic/sic_8xxx_enable.D 28.700
use_cart_logic/cfg_mode<1>.Q use_cart_logic/sic_axxx_enable.D 28.700
use_cart_logic/cfg_mode<2>.Q use_cart_logic/sic_8xxx_enable.D 28.700
use_cart_logic/cfg_mode<2>.Q use_cart_logic/sic_axxx_enable.D 28.700
use_cart_logic/cfg_mode<3>.Q use_cart_logic/sic_8xxx_enable.D 28.700
use_cart_logic/cfg_mode<3>.Q use_cart_logic/sic_axxx_enable.D 28.700
use_cart_logic/cfg_mode<4>.Q use_cart_logic/sic_8xxx_enable.D 28.700
use_cart_logic/cfg_mode<4>.Q use_cart_logic/sic_axxx_enable.D 28.700
use_cart_logic/cfg_mode<5>.Q use_cart_logic/sic_8xxx_enable.D 28.700
use_cart_logic/cfg_mode<5>.Q use_cart_logic/sic_axxx_enable.D 28.700
eeprom_cs.Q eeprom_cs.D 16.500
eeprom_sck.Q eeprom_sck.D 16.500
eeprom_si.Q eeprom_si.D 16.500
mod_en.Q mod_en.D 16.500
reset_n_sync.Q use_cart_logic/cfg_bank2<16>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_bank2<21>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_bank2<23>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_bank2<24>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_bank2<25>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_bank2<26>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_bank<21>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_bank<22>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_bank<23>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_bank<24>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_bank<25>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_bank<26>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_enable2.D 16.500
reset_n_sync.Q use_cart_logic/cfg_mode<1>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_mode<2>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_mode<3>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_mode<4>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_mode<5>.D 16.500
reset_n_sync.Q use_cart_logic/cfg_source_ram.D 16.500
reset_n_sync.Q use_cart_logic/cfg_source_ram2.D 16.500
reset_n_sync.Q use_cart_logic/cfg_write_enable2.D 16.500
reset_n_sync.Q use_cart_logic/oss_bank<0>.D 16.500
reset_n_sync.Q use_cart_logic/oss_bank<1>.D 16.500
use_cart_logic/cfg_bank2<16>.Q use_cart_logic/cfg_bank2<16>.D 16.500
use_cart_logic/cfg_bank2<21>.Q use_cart_logic/cfg_bank2<21>.D 16.500
use_cart_logic/cfg_bank2<23>.Q use_cart_logic/cfg_bank2<23>.D 16.500
use_cart_logic/cfg_bank2<24>.Q use_cart_logic/cfg_bank2<24>.D 16.500
use_cart_logic/cfg_bank2<25>.Q use_cart_logic/cfg_bank2<25>.D 16.500
use_cart_logic/cfg_bank2<26>.Q use_cart_logic/cfg_bank2<26>.D 16.500
use_cart_logic/cfg_bank<14>.Q use_cart_logic/cfg_bank<14>.D 16.500
use_cart_logic/cfg_bank<15>.Q use_cart_logic/cfg_bank<15>.D 16.500
use_cart_logic/cfg_bank<17>.Q use_cart_logic/cfg_bank<17>.D 16.500
use_cart_logic/cfg_bank<18>.Q use_cart_logic/cfg_bank<18>.D 16.500
use_cart_logic/cfg_bank<19>.Q use_cart_logic/cfg_bank<19>.D 16.500
use_cart_logic/cfg_bank<20>.Q use_cart_logic/cfg_bank<20>.D 16.500
use_cart_logic/cfg_bank<21>.Q use_cart_logic/cfg_bank<21>.D 16.500
use_cart_logic/cfg_bank<24>.Q use_cart_logic/cfg_bank<24>.D 16.500
use_cart_logic/cfg_bank<25>.Q use_cart_logic/cfg_bank<25>.D 16.500
use_cart_logic/cfg_enable2.Q use_cart_logic/cfg_enable2.D 16.500
use_cart_logic/cfg_mode<0>.Q use_cart_logic/cfg_mode<0>.D 16.500
use_cart_logic/cfg_mode<1>.Q use_cart_logic/cfg_mode<1>.D 16.500
use_cart_logic/cfg_mode<2>.Q use_cart_logic/cfg_mode<2>.D 16.500
use_cart_logic/cfg_mode<3>.Q use_cart_logic/cfg_mode<3>.D 16.500
use_cart_logic/cfg_mode<4>.Q use_cart_logic/cfg_mode<4>.D 16.500
use_cart_logic/cfg_mode<5>.Q use_cart_logic/cfg_mode<5>.D 16.500
use_cart_logic/cfg_source_ram.Q use_cart_logic/cfg_source_ram.D 16.500
use_cart_logic/cfg_write_enable2.Q use_cart_logic/cfg_write_enable2.D 16.500
use_cart_logic/oss_bank<0>.Q use_cart_logic/oss_bank<0>.D 16.500
use_cart_logic/oss_bank<1>.Q use_cart_logic/oss_bank<1>.D 16.500
reset_n_sync.Q mod_en.D 15.500
reset_n_sync.Q use_cart_logic/cfg_bank2<13>.D 15.500
reset_n_sync.Q use_cart_logic/cfg_bank2<14>.D 15.500
reset_n_sync.Q use_cart_logic/cfg_bank2<15>.D 15.500
reset_n_sync.Q use_cart_logic/cfg_bank2<17>.D 15.500
reset_n_sync.Q use_cart_logic/cfg_bank2<18>.D 15.500
reset_n_sync.Q use_cart_logic/cfg_bank2<19>.D 15.500
reset_n_sync.Q use_cart_logic/cfg_bank2<20>.D 15.500
reset_n_sync.Q use_cart_logic/cfg_bank2<22>.D 15.500
reset_n_sync.Q use_cart_logic/cfg_enable.D 15.500
reset_n_sync.Q use_cart_logic/cfg_mode<0>.D 15.500
reset_n_sync.Q use_cart_logic/sic_8xxx_enable.D 15.500
reset_n_sync.Q use_cart_logic/sic_axxx_enable.D 15.500
reset_n_sync1.Q reset_n_sync.D 15.500
use_cart_logic/cfg_bank2<13>.Q use_cart_logic/cfg_bank2<13>.D 15.500
use_cart_logic/cfg_bank2<14>.Q use_cart_logic/cfg_bank2<14>.D 15.500
use_cart_logic/cfg_bank2<15>.Q use_cart_logic/cfg_bank2<15>.D 15.500
use_cart_logic/cfg_bank2<17>.Q use_cart_logic/cfg_bank2<17>.D 15.500
use_cart_logic/cfg_bank2<18>.Q use_cart_logic/cfg_bank2<18>.D 15.500
use_cart_logic/cfg_bank2<19>.Q use_cart_logic/cfg_bank2<19>.D 15.500
use_cart_logic/cfg_bank2<20>.Q use_cart_logic/cfg_bank2<20>.D 15.500
use_cart_logic/cfg_bank2<22>.Q use_cart_logic/cfg_bank2<22>.D 15.500
use_cart_logic/cfg_bank<22>.Q use_cart_logic/cfg_bank<22>.D 15.500
use_cart_logic/cfg_bank<23>.Q use_cart_logic/cfg_bank<23>.D 15.500
use_cart_logic/cfg_bank<26>.Q use_cart_logic/cfg_bank<26>.D 15.500
use_cart_logic/cfg_source_ram2.Q use_cart_logic/cfg_source_ram2.D 15.500
use_cart_logic/sic_8xxx_enable.Q use_cart_logic/sic_8xxx_enable.D 15.500
use_cart_logic/sic_axxx_enable.Q use_cart_logic/sic_axxx_enable.D 15.500
reset_n_sync.Q rom_reset.CE 10.000


Pad to Pad List

Source Pad Destination Pad Delay
adr<4> data<0> 51.600
adr<4> data<1> 51.600
adr<4> data<2> 51.600
adr<4> data<3> 51.600
adr<4> data<4> 51.600
adr<4> data<5> 51.600
adr<4> data<6> 51.600
adr<4> data<7> 51.600
adr<5> data<0> 51.600
adr<5> data<1> 51.600
adr<5> data<2> 51.600
adr<5> data<3> 51.600
adr<5> data<4> 51.600
adr<5> data<5> 51.600
adr<5> data<6> 51.600
adr<5> data<7> 51.600
adr<6> data<0> 51.600
adr<6> data<1> 51.600
adr<6> data<2> 51.600
adr<6> data<3> 51.600
adr<6> data<4> 51.600
adr<6> data<5> 51.600
adr<6> data<6> 51.600
adr<6> data<7> 51.600
adr<7> data<0> 51.600
adr<7> data<1> 51.600
adr<7> data<2> 51.600
adr<7> data<3> 51.600
adr<7> data<4> 51.600
adr<7> data<5> 51.600
adr<7> data<6> 51.600
adr<7> data<7> 51.600
cctl data<0> 51.600
cctl data<1> 51.600
cctl data<2> 51.600
cctl data<3> 51.600
cctl data<4> 51.600
cctl data<5> 51.600
cctl data<6> 51.600
cctl data<7> 51.600
adr<0> data<0> 37.400
adr<0> data<1> 37.400
adr<0> data<2> 37.400
adr<0> data<3> 37.400
adr<0> data<4> 37.400
adr<0> data<5> 37.400
adr<0> data<6> 37.400
adr<0> data<7> 37.400
adr<1> data<0> 37.400
adr<1> data<1> 37.400
adr<1> data<2> 37.400
adr<1> data<3> 37.400
adr<1> data<4> 37.400
adr<1> data<5> 37.400
adr<1> data<6> 37.400
adr<1> data<7> 37.400
adr<2> data<0> 37.400
adr<2> data<1> 37.400
adr<2> data<2> 37.400
adr<2> data<3> 37.400
adr<2> data<4> 37.400
adr<2> data<5> 37.400
adr<2> data<6> 37.400
adr<2> data<7> 37.400
adr<3> data<0> 37.400
adr<3> data<1> 37.400
adr<3> data<2> 37.400
adr<3> data<3> 37.400
adr<3> data<4> 37.400
adr<3> data<5> 37.400
adr<3> data<6> 37.400
adr<3> data<7> 37.400
rw data<0> 37.400
rw data<1> 37.400
rw data<2> 37.400
rw data<3> 37.400
rw data<4> 37.400
rw data<5> 37.400
rw data<6> 37.400
rw data<7> 37.400
s4 data<0> 37.400
s4 data<1> 37.400
s4 data<2> 37.400
s4 data<3> 37.400
s4 data<4> 37.400
s4 data<5> 37.400
s4 data<6> 37.400
s4 data<7> 37.400
s4 ram_ce 34.200
s4 ram_rom_adr<13> 34.200
s4 ram_rom_adr<15> 34.200
s4 ram_rom_adr<19> 34.200
s4 ram_rom_adr<22> 34.200
s4 ram_rom_adr<24> 34.200
s4 ram_rom_adr<26> 34.200
s4 rom_ce 34.200
s4 ram_rom_adr<14> 33.200
s4 ram_rom_adr<16> 33.200
s4 ram_rom_adr<17> 33.200
s4 ram_rom_adr<18> 33.200
s4 ram_rom_adr<20> 33.200
s4 ram_rom_adr<21> 33.200
s4 ram_rom_adr<23> 33.200
s4 ram_rom_adr<25> 33.200
s5 data<0> 24.200
s5 data<1> 24.200
s5 data<2> 24.200
s5 data<3> 24.200
s5 data<4> 24.200
s5 data<5> 24.200
s5 data<6> 24.200
s5 data<7> 24.200
adr<11> ram_rom_adr<11> 21.000
adr<12> ram_rom_adr<12> 21.000
adr<12> ram_rom_adr<13> 21.000
adr<1> ram_rom_adr<1> 21.000
adr<4> ram_rom_adr<4> 21.000
adr<7> ram_rom_adr<7> 21.000
adr<8> ram_rom_adr<8> 21.000
phi2 ram_rom_oe 21.000
rw ram_ce 21.000
rw ram_rom_oe 21.000
rw rom_ce 21.000
s5 ram_ce 21.000
s5 ram_rom_adr<14> 21.000
s5 ram_rom_adr<15> 21.000
s5 ram_rom_adr<19> 21.000
s5 rom_ce 21.000
adr<0> ram_rom_adr<0> 20.000
adr<10> ram_rom_adr<10> 20.000
adr<2> ram_rom_adr<2> 20.000
adr<3> ram_rom_adr<3> 20.000
adr<5> ram_rom_adr<5> 20.000
adr<6> ram_rom_adr<6> 20.000
adr<9> ram_rom_adr<9> 20.000
eeprom_so data<7> 20.000
phi2short ram_rom_we 20.000
ram_rom_data<0> data<0> 20.000
ram_rom_data<1> data<1> 20.000
ram_rom_data<2> data<2> 20.000
ram_rom_data<3> data<3> 20.000
ram_rom_data<4> data<4> 20.000
ram_rom_data<5> data<5> 20.000
ram_rom_data<6> data<6> 20.000
ram_rom_data<7> data<7> 20.000
rw ram_rom_we 20.000
s5 ram_rom_adr<13> 20.000
s5 ram_rom_adr<16> 20.000
s5 ram_rom_adr<17> 20.000
s5 ram_rom_adr<18> 20.000
data<4> ram_rom_data<4> 17.500
data<0> ram_rom_data<0> 16.500
data<1> ram_rom_data<1> 16.500
data<2> ram_rom_data<2> 16.500
data<3> ram_rom_data<3> 16.500
data<5> ram_rom_data<5> 16.500
data<6> ram_rom_data<6> 16.500
data<7> ram_rom_data<7> 16.500
rw ram_rom_data<0> 11.000
rw ram_rom_data<1> 11.000
rw ram_rom_data<2> 11.000
rw ram_rom_data<3> 11.000
rw ram_rom_data<4> 11.000
rw ram_rom_data<5> 11.000
rw ram_rom_data<6> 11.000
rw ram_rom_data<7> 11.000



Number of paths analyzed: 1187
Number of Timing errors: 1187
Analysis Completed: Sun Oct 27 13:13:43 2013