Signal Name | Total Pterms | Total Inputs | Function Block | Macrocell | Power Mode | Slew Rate | Pin Number | Pin Type | Pin Use | Reg Init State |
---|---|---|---|---|---|---|---|---|---|---|
$OpTx$FX_DC$6 | 1 | 4 | FB1 | MC1 | LOW | (b) | (b) | |||
data<0> | 10 | 15 | FB1 | MC2 | LOW | SLOW | 11 | I/O | I/O | |
data<7> | 5 | 11 | FB1 | MC3 | LOW | SLOW | 12 | I/O | I/O | |
use_cart_logic/cfg_bank2<20> | 3 | 7 | FB1 | MC4 | LOW | (b) | (b) | RESET | ||
data<6> | 4 | 9 | FB1 | MC5 | LOW | SLOW | 13 | I/O | I/O | |
use_cart_logic/cfg_bank2<15> | 3 | 7 | FB1 | MC6 | LOW | 14 | I/O | I | RESET | |
use_cart_logic/cfg_bank2<14> | 3 | 7 | FB1 | MC7 | LOW | (b) | (b) | RESET | ||
use_cart_logic/cfg_bank2<13> | 3 | 7 | FB1 | MC8 | LOW | 15 | I/O | I | RESET | |
eeprom_cs | 4 | 11 | FB1 | MC9 | LOW | SLOW | 16 | I/O | O | SET |
use_cart_logic/cfg_mode<5> | 5 | 11 | FB1 | MC10 | LOW | (b) | (b) | RESET | ||
use_cart_logic/cfg_mode<4> | 5 | 11 | FB1 | MC11 | LOW | 17 | I/O | I | RESET | |
eeprom_sck | 4 | 11 | FB1 | MC12 | LOW | SLOW | 18 | I/O | O | RESET |
use_cart_logic/cfg_write_enable2 | 6 | 11 | FB1 | MC13 | LOW | (b) | (b) | RESET | ||
use_cart_logic/cfg_source_ram | 6 | 11 | FB1 | MC14 | LOW | 19 | I/O | (b) | RESET | |
eeprom_si | 4 | 11 | FB1 | MC15 | LOW | SLOW | 20 | I/O | O | RESET |
use_cart_logic/cfg_enable2 | 6 | 8 | FB1 | MC16 | LOW | (b) | (b) | RESET | ||
use_cart_logic/cfg_bank<23> | 6 | 11 | FB1 | MC17 | LOW | 22 | I/O/GCK1 | I | RESET | |
use_cart_logic/cfg_bank<13> | 6 | 10 | FB1 | MC18 | LOW | (b) | (b) | RESET | ||
use_cart_logic/cfg_bank<25> | 6 | 11 | FB2 | MC1 | LOW | (b) | (b) | RESET | ||
use_cart_logic/cfg_bank<26> | 6 | 11 | FB2 | MC3 | LOW | (b) | (b) | RESET | ||
use_cart_logic/cfg_source_ram2 | 6 | 11 | FB2 | MC4 | LOW | (b) | (b) | RESET | ||
data<4> | 7 | 12 | FB2 | MC5 | LOW | SLOW | 1 | I/O/GTS3 | I/O | |
use_cart_logic/cfg_bank2<24> | 5 | 12 | FB2 | MC6 | LOW | 2 | I/O/GTS4 | (b) | RESET | |
use_cart_logic/cfg_bank2<25> | 5 | 12 | FB2 | MC7 | LOW | (b) | (b) | RESET | ||
use_cart_logic/cfg_bank2<26> | 5 | 12 | FB2 | MC8 | LOW | 3 | I/O/GTS1 | I | RESET | |
use_cart_logic/cfg_mode<3> | 5 | 11 | FB2 | MC9 | LOW | 4 | I/O/GTS2 | I | RESET | |
use_cart_logic/cfg_bank2<16> | 3 | 7 | FB2 | MC10 | LOW | (b) | (b) | RESET | ||
data<5> | 7 | 12 | FB2 | MC11 | LOW | SLOW | 6 | I/O | I/O | |
use_cart_logic/SFDecomp_1040/use_cart_logic/SFDecomp_1040_D2 | 1 | 4 | FB2 | MC12 | LOW | 7 | I/O | (b) | ||
data<2> | 8 | 13 | FB2 | MC14 | LOW | SLOW | 8 | I/O | I/O | |
data<1> | 8 | 13 | FB2 | MC15 | LOW | SLOW | 9 | I/O | I/O | |
data<3> | 8 | 13 | FB2 | MC17 | LOW | SLOW | 10 | I/O | I/O | |
use_cart_logic/cfg_bank<24> | 6 | 11 | FB2 | MC18 | LOW | (b) | (b) | RESET | ||
$OpTx$FX_DC$22 | 1 | 3 | FB3 | MC1 | LOW | (b) | (b) | |||
use_cart_logic/cfg_bank<20> | 11 | 15 | FB3 | MC2 | LOW | 23 | I/O/GCK2 | GCK/I | RESET | |
use_cart_logic/N145/use_cart_logic/N145_D2 | 7 | 10 | FB3 | MC3 | LOW | (b) | (b) | |||
use_cart_logic/oss_bank<1> | 6 | 12 | FB3 | MC4 | LOW | (b) | (b) | RESET | ||
ram_rom_adr<26> | 2 | 3 | FB3 | MC5 | LOW | SLOW | 24 | I/O | O | |
ram_rom_adr<0> | 1 | 1 | FB3 | MC6 | LOW | SLOW | 25 | I/O | O | |
$OpTx$FX_DC$107 | 5 | 11 | FB3 | MC7 | LOW | (b) | (b) | |||
use_cart_logic/sic_axxx_enable | 3 | 6 | FB3 | MC8 | LOW | 27 | I/O/GCK3 | I | SET | |
ram_rom_adr<17> | 4 | 9 | FB3 | MC9 | LOW | SLOW | 28 | I/O | O | |
$OpTx$FX_DC$42 | 2 | 3 | FB3 | MC10 | LOW | (b) | (b) | |||
ram_rom_adr<25> | 2 | 3 | FB3 | MC11 | LOW | SLOW | 29 | I/O | O | |
rom_reset | 1 | 1 | FB3 | MC12 | LOW | SLOW | 30 | I/O | O | RESET |
$OpTx$FX_SC$112 | 2 | 4 | FB3 | MC13 | LOW | (b) | (b) | |||
ram_rom_data<7> | 2 | 2 | FB3 | MC14 | LOW | SLOW | 32 | I/O | I/O | |
ram_rom_data<6> | 2 | 2 | FB3 | MC15 | LOW | SLOW | 33 | I/O | I/O | |
use_cart_logic/N230/use_cart_logic/N230_D2 | 2 | 5 | FB3 | MC16 | LOW | (b) | (b) | |||
use_cart_logic/cfg_enable | 15 | 20 | FB3 | MC17 | LOW | 34 | I/O | (b) | SET | |
use_cart_logic/cfg_bank_13_cmp_eq0005/use_cart_logic/cfg_bank_13_cmp_eq0005_D2 | 1 | 8 | FB4 | MC1 | LOW | (b) | (b) | |||
reset_n_sync1 | 1 | 1 | FB4 | MC2 | LOW | 87 | I/O | I | RESET | |
reset_n_sync | 1 | 1 | FB4 | MC3 | LOW | (b) | (b) | RESET | ||
$OpTx$FX_DC$7 | 1 | 2 | FB4 | MC4 | LOW | (b) | (b) | |||
$OpTx$FX_DC$56 | 1 | 2 | FB4 | MC5 | LOW | 89 | I/O | I | ||
$OpTx$FX_DC$36 | 1 | 2 | FB4 | MC6 | LOW | 90 | I/O | I | ||
$OpTx$FX_DC$23 | 1 | 2 | FB4 | MC7 | LOW | (b) | (b) | |||
$OpTx$FX_DC$137 | 1 | 2 | FB4 | MC8 | LOW | 91 | I/O | I | ||
data_or0000/data_or0000_D2 | 2 | 7 | FB4 | MC9 | LOW | 92 | I/O | I | ||
$OpTx$FX_DC$9 | 2 | 5 | FB4 | MC10 | LOW | (b) | (b) | |||
$OpTx$FX_DC$43 | 2 | 5 | FB4 | MC11 | LOW | 93 | I/O | I | ||
$OpTx$FX_DC$33 | 2 | 5 | FB4 | MC12 | LOW | 94 | I/O | I | ||
use_cart_logic/sic_8xxx_enable | 3 | 6 | FB4 | MC13 | LOW | (b) | (b) | RESET | ||
use_cart_logic/cfg_bank2<19> | 3 | 7 | FB4 | MC14 | LOW | 95 | I/O | I | RESET | |
use_cart_logic/cfg_bank2<18> | 3 | 7 | FB4 | MC15 | LOW | 96 | I/O | I | RESET | |
use_cart_logic/cfg_bank2<17> | 3 | 7 | FB4 | MC16 | LOW | (b) | (b) | RESET | ||
data_1_IOBUFE/data_1_IOBUFE_TRST | 3 | 7 | FB4 | MC17 | LOW | 97 | I/O | I | ||
$OpTx$INV$3 | 8 | 10 | FB4 | MC18 | LOW | (b) | (b) | |||
use_cart_logic/cfg_bank<14> | 15 | 27 | FB5 | MC1 | LOW | (b) | (b) | RESET | ||
ram_rom_data<5> | 2 | 2 | FB5 | MC2 | LOW | SLOW | 35 | I/O | I/O | |
use_cart_logic/cfg_bank<16> | 14 | 21 | FB5 | MC4 | LOW | (b) | (b) | RESET | ||
ram_rom_data<4> | 2 | 2 | FB5 | MC5 | LOW | SLOW | 36 | I/O | I/O | |
ram_rom_data<3> | 2 | 2 | FB5 | MC6 | LOW | SLOW | 37 | I/O | I/O | |
$OpTx$FX_DC$124 | 1 | 6 | FB5 | MC7 | LOW | (b) | (b) | |||
ram_rom_data<2> | 2 | 2 | FB5 | MC8 | LOW | SLOW | 39 | I/O | I/O | |
ram_rom_data<1> | 2 | 2 | FB5 | MC9 | LOW | SLOW | 40 | I/O | I/O | |
use_cart_logic/SFDecomp_1084/use_cart_logic/SFDecomp_1084_D2 | 5 | 5 | FB5 | MC10 | LOW | (b) | (b) | |||
ram_rom_data<0> | 2 | 2 | FB5 | MC11 | LOW | SLOW | 41 | I/O | I/O | |
ram_rom_oe | 1 | 2 | FB5 | MC12 | LOW | SLOW | 42 | I/O | O | |
use_cart_logic/cfg_bank<15> | 15 | 26 | FB5 | MC13 | LOW | (b) | (b) | RESET | ||
ram_rom_adr<1> | 1 | 1 | FB5 | MC14 | LOW | SLOW | 43 | I/O | O | |
$OpTx$FX_DC$35 | 2 | 4 | FB5 | MC15 | LOW | 46 | I/O | (b) | ||
rom_ce | 8 | 12 | FB5 | MC17 | LOW | SLOW | 49 | I/O | O | |
$OpTx$BIN_OR$350 | 13 | 23 | FB6 | MC1 | LOW | (b) | (b) | |||
ram_rom_adr<15> | 6 | 9 | FB6 | MC2 | LOW | SLOW | 74 | I/O | O | |
use_cart_logic/cfg_bank_13_and0008/use_cart_logic/cfg_bank_13_and0008_D2 | 1 | 7 | FB6 | MC3 | LOW | (b) | (b) | |||
$OpTx$FX_DC$19 | 1 | 6 | FB6 | MC4 | LOW | (b) | (b) | |||
ram_rom_adr<16> | 4 | 8 | FB6 | MC5 | LOW | SLOW | 76 | I/O | O | |
ram_rom_adr<23> | 2 | 3 | FB6 | MC6 | LOW | SLOW | 77 | I/O | O | |
use_cart_logic/N26/use_cart_logic/N26_D2 | 3 | 5 | FB6 | MC7 | LOW | (b) | (b) | |||
ram_rom_adr<24> | 2 | 3 | FB6 | MC8 | LOW | SLOW | 78 | I/O | O | |
rd5 | 9 | 11 | FB6 | MC9 | LOW | SLOW | 79 | I/O | O | |
$OpTx$FX_DC$71 | 3 | 7 | FB6 | MC10 | LOW | (b) | (b) | |||
$OpTx$FX_DC$70 | 3 | 13 | FB6 | MC11 | LOW | 80 | I/O | (b) | ||
rd4 | 6 | 9 | FB6 | MC12 | LOW | SLOW | 81 | I/O | O | |
$OpTx$FX_DC$30 | 3 | 9 | FB6 | MC13 | LOW | (b) | (b) | |||
$OpTx$FX_DC$84 | 4 | 13 | FB6 | MC14 | LOW | 82 | I/O | I | ||
ram_ce | 6 | 12 | FB6 | MC15 | LOW | SLOW | 85 | I/O | O | |
use_cart_logic/oss_bank<0> | 6 | 12 | FB6 | MC16 | LOW | (b) | (b) | RESET | ||
use_cart_logic/N19/use_cart_logic/N19_D2 | 7 | 8 | FB6 | MC17 | LOW | 86 | I/O | I | ||
use_cart_logic/cfg_bank_14_and0000/use_cart_logic/cfg_bank_14_and0000_D2 | 1 | 8 | FB6 | MC18 | LOW | (b) | (b) | |||
$OpTx$INV$2 | 4 | 6 | FB7 | MC1 | LOW | (b) | (b) | |||
ram_rom_we | 1 | 2 | FB7 | MC2 | LOW | SLOW | 50 | I/O | O | |
$OpTx$FX_DC$158 | 3 | 6 | FB7 | MC3 | LOW | (b) | (b) | |||
use_cart_logic/cfg_bank<18> | 11 | 20 | FB7 | MC4 | LOW | (b) | (b) | RESET | ||
ram_rom_adr<2> | 1 | 1 | FB7 | MC5 | LOW | SLOW | 52 | I/O | O | |
ram_rom_adr<3> | 1 | 1 | FB7 | MC6 | LOW | SLOW | 53 | I/O | O | |
use_cart_logic/cfg_bank<19> | 14 | 20 | FB7 | MC7 | LOW | (b) | (b) | RESET | ||
ram_rom_adr<4> | 1 | 1 | FB7 | MC8 | LOW | SLOW | 54 | I/O | O | |
ram_rom_adr<5> | 1 | 1 | FB7 | MC9 | LOW | SLOW | 55 | I/O | O | |
ram_rom_adr<6> | 1 | 1 | FB7 | MC11 | LOW | SLOW | 56 | I/O | O | |
ram_rom_adr<7> | 1 | 1 | FB7 | MC12 | LOW | SLOW | 58 | I/O | O | |
use_cart_logic/cfg_bank<17> | 15 | 22 | FB7 | MC13 | LOW | (b) | (b) | RESET | ||
ram_rom_adr<8> | 1 | 1 | FB7 | MC14 | LOW | SLOW | 59 | I/O | O | |
ram_rom_adr<18> | 3 | 8 | FB7 | MC15 | LOW | SLOW | 60 | I/O | O | |
ram_rom_adr<19> | 3 | 9 | FB7 | MC17 | LOW | SLOW | 61 | I/O | O | |
$OpTx$BIN_STEP$349 | 15 | 28 | FB7 | MC18 | LOW | (b) | (b) | |||
use_cart_logic/cfg_mode<2> | 5 | 11 | FB8 | MC1 | LOW | (b) | (b) | RESET | ||
ram_rom_adr<22> | 2 | 3 | FB8 | MC2 | LOW | SLOW | 63 | I/O | O | |
use_cart_logic/cfg_mode<1> | 5 | 11 | FB8 | MC3 | LOW | (b) | (b) | RESET | ||
use_cart_logic/cfg_bank2<23> | 5 | 12 | FB8 | MC4 | LOW | (b) | (b) | RESET | ||
ram_rom_adr<21> | 2 | 3 | FB8 | MC5 | LOW | SLOW | 64 | I/O | O | |
ram_rom_adr<20> | 2 | 3 | FB8 | MC6 | LOW | SLOW | 65 | I/O | O | |
use_cart_logic/cfg_bank2<22> | 5 | 12 | FB8 | MC7 | LOW | (b) | (b) | RESET | ||
ram_rom_adr<9> | 1 | 1 | FB8 | MC8 | LOW | SLOW | 66 | I/O | O | |
ram_rom_adr<10> | 1 | 1 | FB8 | MC9 | LOW | SLOW | 67 | I/O | O | |
use_cart_logic/cfg_bank2<21> | 5 | 12 | FB8 | MC10 | LOW | (b) | (b) | RESET | ||
ram_rom_adr<11> | 1 | 1 | FB8 | MC11 | LOW | SLOW | 68 | I/O | O | |
ram_rom_adr<12> | 5 | 7 | FB8 | MC12 | LOW | SLOW | 70 | I/O | O | |
use_cart_logic/cfg_mode<0> | 6 | 11 | FB8 | MC13 | LOW | (b) | (b) | SET | ||
ram_rom_adr<13> | 12 | 15 | FB8 | MC14 | LOW | SLOW | 71 | I/O | O | |
ram_rom_adr<14> | 3 | 7 | FB8 | MC15 | LOW | SLOW | 72 | I/O | O | |
use_cart_logic/cfg_bank<22> | 6 | 11 | FB8 | MC16 | LOW | (b) | (b) | RESET | ||
mod_en | 6 | 11 | FB8 | MC17 | LOW | SLOW | 73 | I/O | O | SET |
use_cart_logic/cfg_bank<21> | 6 | 11 | FB8 | MC18 | LOW | (b) | (b) | RESET |