Equations

********** Mapped Logic **********
$OpTx$FX_DC$444 <= (cfg_mode(2) AND cfg_mode(1));
$OpTx$FX_DC$451 <= (NOT cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(1));
$OpTx$FX_DC$457 <= (NOT adr(6) AND NOT adr(5) AND NOT adr(4));
$OpTx$FX_DC$483 <= (cfg_mode(2) AND NOT cfg_mode(3) AND
      use_cart_logic/N11/use_cart_logic/N11_D2);
$OpTx$FX_DC$490 <= ((NOT cfg_mode(2) AND NOT cfg_mode(1) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2)
      OR (NOT cfg_mode(5) AND cfg_mode(4) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2)
      OR (cfg_mode(2) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT N247/N247_D2)
      OR (rw AND cfg_mode(4)));
$OpTx$FX_DC$504 <= ((NOT cfg_mode(0) AND NOT cfg_mode(5) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2)
      OR (cfg_mode(2) AND NOT cfg_mode(5) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2)
      OR (NOT cfg_mode(2) AND cfg_mode(3) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2)
      OR (cfg_mode(4) AND cfg_mode(1) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2)
      OR (NOT cfg_mode(3) AND NOT cfg_mode(4) AND adr(7) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2));
$OpTx$INV$431 <= ((cfg_mode(5) AND cfg_mode(3) AND data(7).PIN)
      OR (cfg_mode(5) AND data(7).PIN AND data(2).PIN AND
      data(1).PIN AND data(0).PIN AND data(5).PIN AND data(4).PIN AND
      data(3).PIN AND data(6).PIN)
      OR (rw AND cfg_mode(5))
      OR (adr(3) AND NOT cfg_mode(5))
      OR (NOT cfg_mode(5) AND NOT cfg_mode(3))
      OR (NOT cfg_mode(5) AND adr(4)));
$OpTx$INV$433 <= ((rw)
      OR (cfg_write_enable AND
      use_cart_logic/N23/use_cart_logic/N23_D2)
      OR (cfg_write_enable2 AND
      use_cart_logic/N16/use_cart_logic/N16_D2));
N140/N140_D2 <= ((NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cctl AND N41/N41_D2)
      OR (NOT cfg_mode(3) AND NOT cfg_mode(4) AND NOT cctl AND N41/N41_D2)
      OR (NOT rw AND cfg_mode(0) AND NOT cfg_mode(5) AND NOT cctl AND
      NOT cctl_access_and0000/cctl_access_and0000_D2)
      OR (cfg_mode(0) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cctl AND
      NOT cctl_access_and0000/cctl_access_and0000_D2)
      OR (NOT rw AND NOT cctl AND N41/N41_D2));
N219/N219_D2 <= ((cfg_mode(2) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND
      adr(5))
      OR (NOT cfg_mode(5) AND NOT cfg_mode(3) AND adr(4) AND
      NOT use_cart_logic/N69/use_cart_logic/N69_D2)
      OR (NOT cfg_mode(5) AND cfg_mode(1) AND
      NOT use_cart_logic/N252/use_cart_logic/N252_D2 AND NOT use_cart_logic/N69/use_cart_logic/N69_D2)
      OR (cfg_mode(2) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND
      adr(6))
      OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT adr(6) AND
      NOT use_cart_logic/N69/use_cart_logic/N69_D2)
      OR (cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND
      NOT cfg_mode(3) AND NOT cfg_mode(4))
      OR (cfg_mode(0) AND NOT cfg_mode(5) AND cfg_mode(3) AND
      NOT use_cart_logic/N252/use_cart_logic/N252_D2 AND NOT use_cart_logic/N69/use_cart_logic/N69_D2)
      OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND
      NOT adr(5) AND NOT use_cart_logic/N69/use_cart_logic/N69_D2)
      OR (NOT cfg_mode(5) AND cfg_mode(4))
      OR (cfg_mode(2) AND NOT cfg_mode(3) AND cfg_mode(1))
      OR (cfg_mode(2) AND cfg_mode(4) AND cfg_mode(1))
      OR (NOT cfg_mode(3) AND NOT cfg_mode(4) AND adr(7))
      OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND
      NOT adr(7)));
N247/N247_D2 <= (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(3) AND
      NOT cfg_mode(4) AND NOT cfg_mode(1) AND NOT adr(6) AND NOT adr(7) AND NOT adr(5));
N41/N41_D2 <= ((NOT rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1))
      OR (NOT rw AND NOT cctl AND
      NOT cctl_access_and0000/cctl_access_and0000_D2)
      OR (NOT cfg_mode(2) AND NOT cctl AND
      NOT cctl_access_and0000/cctl_access_and0000_D2));
cctl_access_and0000/cctl_access_and0000_D2 <= (NOT mod_en AND NOT adr(6) AND adr(7) AND adr(5) AND NOT adr(4));
FDCPE_cfg_bank213: FDCPE port map (cfg_bank2(13),cfg_bank2_D(13),NOT phi2short,'0','0');
     cfg_bank2_D(13) <= ((cfg_bank2(13) AND
      NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
      OR (data(0).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));
FDCPE_cfg_bank214: FDCPE port map (cfg_bank2(14),cfg_bank2_D(14),NOT phi2short,'0','0');
     cfg_bank2_D(14) <= ((cfg_bank2(14) AND
      NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
      OR (data(1).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));
FDCPE_cfg_bank215: FDCPE port map (cfg_bank2(15),cfg_bank2_D(15),NOT phi2short,'0','0');
     cfg_bank2_D(15) <= ((cfg_bank2(15) AND
      NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
      OR (data(2).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));
FDCPE_cfg_bank216: FDCPE port map (cfg_bank2(16),cfg_bank2_D(16),NOT phi2short,'0','0');
     cfg_bank2_D(16) <= ((cfg_bank2(16) AND
      NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
      OR (data(3).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));
FDCPE_cfg_bank217: FDCPE port map (cfg_bank2(17),cfg_bank2_D(17),NOT phi2short,'0','0');
     cfg_bank2_D(17) <= ((cfg_bank2(17) AND
      NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
      OR (data(4).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));
FDCPE_cfg_bank218: FDCPE port map (cfg_bank2(18),cfg_bank2_D(18),NOT phi2short,'0','0');
     cfg_bank2_D(18) <= ((cfg_bank2(18) AND
      NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
      OR (data(5).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));
FDCPE_cfg_bank219: FDCPE port map (cfg_bank2(19),cfg_bank2_D(19),NOT phi2short,'0','0');
     cfg_bank2_D(19) <= ((cfg_bank2(19) AND
      NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
      OR (data(6).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));
FDCPE_cfg_bank220: FDCPE port map (cfg_bank2(20),cfg_bank2_D(20),NOT phi2short,'0','0');
     cfg_bank2_D(20) <= ((cfg_bank2(20) AND
      NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
      OR (data(7).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));
FDCPE_cfg_bank221: FDCPE port map (cfg_bank2(21),cfg_bank2_D(21),NOT phi2short,'0','0');
     cfg_bank2_D(21) <= ((cfg_bank2(21) AND
      NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)
      OR (data(0).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2));
FDCPE_cfg_bank222: FDCPE port map (cfg_bank2(22),cfg_bank2_D(22),NOT phi2short,'0','0');
     cfg_bank2_D(22) <= ((cfg_bank2(22) AND
      NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)
      OR (data(1).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2));
FDCPE_cfg_bank223: FDCPE port map (cfg_bank2(23),cfg_bank2_D(23),NOT phi2short,'0','0');
     cfg_bank2_D(23) <= ((cfg_bank2(23) AND
      NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)
      OR (data(2).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2));
FDCPE_cfg_bank224: FDCPE port map (cfg_bank2(24),cfg_bank2_D(24),NOT phi2short,'0','0');
     cfg_bank2_D(24) <= ((cfg_bank2(24) AND
      NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)
      OR (data(3).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2));
FDCPE_cfg_bank225: FDCPE port map (cfg_bank2(25),cfg_bank2_D(25),NOT phi2short,'0','0');
     cfg_bank2_D(25) <= ((cfg_bank2(25) AND
      NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)
      OR (data(4).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2));
FDCPE_cfg_bank226: FDCPE port map (cfg_bank2(26),cfg_bank2_D(26),NOT phi2short,'0','0');
     cfg_bank2_D(26) <= ((cfg_bank2(26) AND
      NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)
      OR (data(5).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2));
FDCPE_cfg_bank13: FDCPE port map (cfg_bank(13),cfg_bank_D(13),NOT phi2short,'0','0');
     cfg_bank_D(13) <= ((cfg_bank(20).EXP)
      OR (cfg_mode(5) AND cfg_mode(4) AND data(0).PIN AND
      NOT $OpTx$FX_DC$444 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND
      N140/N140_D2)
      OR (NOT cfg_mode(5) AND NOT cfg_mode(3) AND NOT cfg_mode(1) AND
      cfg_bank(13) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (NOT cfg_mode(5) AND cfg_mode(1) AND adr(7) AND
      cfg_bank(13) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(5) AND
      adr(6) AND cfg_bank(13) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (cfg_mode(0) AND cfg_mode(3) AND NOT cfg_mode(4) AND
      cfg_mode(1) AND cfg_bank(13) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (EXP20_.EXP)
      OR (adr(0) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cctl AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND
      use_cart_logic/N69/use_cart_logic/N69_D2)
      OR (cfg_mode(0) AND NOT cfg_mode(5) AND adr(7) AND
      cfg_bank(13) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND NOT use_cart_logic/N252/use_cart_logic/N252_D2)
      OR (cfg_mode(0) AND NOT cfg_mode(5) AND adr(5) AND
      cfg_bank(13) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND NOT use_cart_logic/N69/use_cart_logic/N69_D2)
      OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND
      cfg_bank(13) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND NOT use_cart_logic/N252/use_cart_logic/N252_D2)
      OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT adr(6) AND
      cfg_bank(13) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND NOT use_cart_logic/N69/use_cart_logic/N69_D2)
      OR (reset_n_sync AND cfg_bank(13) AND NOT N140/N140_D2)
      OR (data(0).PIN AND
      cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND
      N140/N140_D2)
      OR (cfg_bank(13) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND $OpTx$FX_DC$444 AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_bank(13) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (NOT cfg_mode(5) AND cfg_mode(4) AND cfg_bank(13) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2));
FDCPE_cfg_bank14: FDCPE port map (cfg_bank(14),cfg_bank_D(14),NOT phi2short,'0','0');
     cfg_bank_D(14) <= ((NOT rw AND cfg_mode(5) AND cfg_mode(4) AND NOT cctl AND
      data(1).PIN AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT $OpTx$FX_DC$444 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT cfg_mode(5) AND cfg_mode(3) AND NOT cfg_mode(4) AND NOT cctl AND
      NOT adr(1) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 AND use_cart_logic/N252/use_cart_logic/N252_D2)
      OR (NOT rw AND cfg_mode(5) AND cfg_mode(3) AND NOT cfg_mode(4) AND
      NOT cctl AND data(0).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT $OpTx$FX_DC$451 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT rw AND NOT cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(5) AND
      NOT cfg_mode(4) AND NOT cfg_mode(1) AND NOT cctl AND data(1).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2)
      OR (adr(0) AND NOT cfg_mode(0) AND NOT cfg_mode(2) AND
      cfg_mode(5) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND
      NOT adr(7) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT cfg_mode(5) AND adr(4) AND cfg_bank(14) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND $OpTx$FX_DC$451 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT cfg_mode(2) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND
      NOT cfg_mode(1) AND cfg_bank(14) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cctl AND adr(1) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 AND use_cart_logic/N69/use_cart_logic/N69_D2)
      OR (NOT rw AND NOT adr(3) AND NOT adr(0) AND NOT cctl AND data(1).PIN AND
      NOT adr(1) AND cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)
      OR (cfg_bank(14) AND
      NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 AND NOT N140/N140_D2)
      OR (cfg_bank(14) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 AND N219/N219_D2)
      OR (NOT rw AND NOT cctl AND data(0).PIN AND N247/N247_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(3) AND
      cfg_bank(14) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_bank(14) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND $OpTx$FX_DC$451 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));
FDCPE_cfg_bank15: FDCPE port map (cfg_bank(15),cfg_bank_D(15),NOT phi2short,'0','0');
     cfg_bank_D(15) <= ((adr(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cctl AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 AND use_cart_logic/N69/use_cart_logic/N69_D2)
      OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(4) AND
      NOT cfg_mode(1) AND cfg_bank(15) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND
      adr(4) AND cfg_bank(15) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT rw AND NOT adr(3) AND NOT adr(2) AND NOT cctl AND data(2).PIN AND
      NOT adr(1) AND cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (rd4_OBUF.EXP)
      OR (NOT adr(2) AND NOT cfg_mode(5) AND cfg_mode(3) AND
      NOT cfg_mode(4) AND NOT cctl AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 AND use_cart_logic/N252/use_cart_logic/N252_D2)
      OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(3) AND
      NOT cfg_mode(4) AND NOT cctl AND data(1).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND
      NOT cfg_mode(1) AND NOT cctl AND data(2).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT rw AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND
      cfg_mode(1) AND NOT cctl AND data(2).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT rw AND cfg_mode(5) AND cfg_mode(3) AND NOT cfg_mode(4) AND
      cfg_mode(1) AND NOT cctl AND data(1).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (cfg_bank(15) AND
      NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 AND NOT N140/N140_D2)
      OR (cfg_bank(15) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 AND N219/N219_D2)
      OR (NOT rw AND NOT cctl AND data(1).PIN AND N247/N247_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT cfg_mode(5) AND NOT cfg_mode(3) AND NOT cfg_mode(1) AND
      cfg_bank(15) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND
      NOT cfg_mode(1) AND cfg_bank(15) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));
FDCPE_cfg_bank16: FDCPE port map (cfg_bank(16),cfg_bank_D(16),NOT phi2short,'0','0');
     cfg_bank_D(16) <= ((adr_0_IBUF$BUF0.EXP)
      OR (cfg_mode(2) AND NOT cfg_mode(5) AND cfg_mode(1) AND
      cfg_bank(16) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (cfg_mode(2) AND cfg_mode(4) AND cfg_mode(1) AND
      cfg_bank(16) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT cfg_mode(3) AND NOT cfg_mode(4) AND adr(7) AND
      cfg_bank(16) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(3) AND
      NOT cfg_mode(4) AND cfg_bank(16) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT cfg_mode(0) AND NOT cfg_mode(5) AND NOT cfg_mode(3) AND
      cfg_bank(16) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2 AND NOT $OpTx$FX_DC$457)
      OR (NOT rw AND NOT adr(3) AND NOT adr(2) AND NOT cctl AND data(3).PIN AND
      NOT adr(1) AND cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (cfg_mode(0) AND cfg_mode(5) AND NOT cfg_mode(3) AND
      NOT cfg_mode(4) AND cfg_bank(16) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT N247/N247_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(3) AND
      NOT cfg_mode(4) AND NOT cctl AND data(2).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND
      NOT cfg_mode(1) AND NOT cctl AND data(3).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT rw AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND
      cfg_mode(1) AND NOT cctl AND data(3).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (cfg_bank(16) AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2 AND $OpTx$FX_DC$490)
      OR (cfg_bank(16) AND
      NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 AND NOT N41/N41_D2)
      OR (rw AND cfg_mode(0) AND cfg_mode(5) AND cfg_bank(16) AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT rw AND NOT cctl AND data(2).PIN AND N247/N247_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (cfg_mode(0) AND NOT cfg_mode(5) AND cfg_mode(3) AND
      cfg_bank(16) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2));
FDCPE_cfg_bank17: FDCPE port map (cfg_bank(17),cfg_bank_D(17),NOT phi2short,'0','0');
     cfg_bank_D(17) <= ((NOT rw AND NOT adr(3) AND NOT adr(2) AND NOT cctl AND data(4).PIN AND
      NOT adr(1) AND cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(3) AND
      NOT cfg_mode(4) AND NOT cctl AND data(3).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND
      NOT cfg_mode(1) AND NOT cctl AND data(4).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT rw AND cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND
      cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND data(4).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (cart_mem_adr(19).EXP)
      OR (NOT cfg_mode(0) AND cfg_mode(4) AND cfg_mode(1) AND
      cfg_bank(17) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (cfg_mode(2) AND cfg_mode(4) AND cfg_mode(1) AND
      cfg_bank(17) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT cfg_mode(2) AND cfg_mode(3) AND NOT cfg_mode(4) AND
      cfg_bank(17) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT cfg_mode(2) AND NOT cfg_mode(4) AND adr(7) AND
      cfg_bank(17) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND
      NOT cfg_mode(4) AND cfg_bank(17) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (cfg_bank(17) AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2 AND $OpTx$FX_DC$490)
      OR (cfg_bank(17) AND
      NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 AND NOT N41/N41_D2)
      OR (NOT rw AND NOT cctl AND data(3).PIN AND N247/N247_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT cfg_mode(0) AND NOT cfg_mode(5) AND cfg_bank(17) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (cfg_mode(2) AND NOT cfg_mode(5) AND cfg_bank(17) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2));
FDCPE_cfg_bank18: FDCPE port map (cfg_bank(18),cfg_bank_D(18),NOT phi2short,'0','0');
     cfg_bank_D(18) <= ((NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(1) AND
      cfg_bank(18) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT N247/N247_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (cfg_mode(2) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND
      cfg_bank(18) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT N247/N247_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT rw AND NOT adr(3) AND NOT adr(2) AND NOT cctl AND data(5).PIN AND
      NOT adr(1) AND cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND
      NOT cfg_mode(1) AND NOT cctl AND data(5).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT rw AND cfg_mode(0) AND cfg_mode(2) AND cfg_mode(5) AND
      cfg_mode(3) AND NOT cfg_mode(4) AND NOT cctl AND data(4).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(3) AND
      NOT cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND data(4).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND
      NOT cfg_mode(3) AND NOT cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND NOT adr(7) AND
      adr(5) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND
      NOT cfg_mode(3) AND NOT cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND NOT adr(7) AND
      adr(4) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (cfg_bank(18) AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2 AND $OpTx$FX_DC$504)
      OR (cfg_bank(18) AND
      NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 AND NOT N41/N41_D2)
      OR (NOT rw AND NOT cctl AND data(4).PIN AND N247/N247_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT cfg_mode(2) AND NOT cfg_mode(1) AND cfg_bank(18) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND
      cfg_bank(18) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2));
FDCPE_cfg_bank19: FDCPE port map (cfg_bank(19),cfg_bank_D(19),NOT phi2short,'0','0');
     cfg_bank_D(19) <= ((NOT cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(3) AND
      cfg_bank(19) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (NOT cfg_mode(4) AND NOT cfg_mode(1) AND cfg_bank(19) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT N247/N247_D2 AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (cfg_mode(0) AND cfg_mode(5) AND NOT cfg_mode(3) AND
      cfg_mode(1) AND cfg_bank(19) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (NOT rw AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
      data(6).PIN AND cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (NOT rw AND cfg_mode(0) AND cfg_mode(2) AND cfg_mode(5) AND
      cfg_mode(4) AND NOT cfg_mode(1) AND NOT cctl AND data(6).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(3) AND
      NOT cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND data(5).PIN AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND
      NOT cfg_mode(3) AND NOT cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND adr(6) AND
      NOT adr(7) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND
      NOT cfg_mode(3) AND NOT cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND NOT adr(7) AND
      adr(5) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (cfg_bank(19) AND
      NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 AND NOT N41/N41_D2)
      OR (cfg_bank(19) AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND $OpTx$FX_DC$504)
      OR (NOT rw AND NOT cctl AND data(5).PIN AND N247/N247_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (NOT cfg_mode(0) AND cfg_mode(4) AND cfg_bank(19) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (NOT cfg_mode(2) AND NOT cfg_mode(1) AND cfg_bank(19) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2));
FDCPE_cfg_bank20: FDCPE port map (cfg_bank(20),cfg_bank_D(20),NOT phi2short,'0','0');
     cfg_bank_D(20) <= ((cfg_bank(21).EXP)
      OR (NOT rw AND NOT cctl AND data(6).PIN AND N247/N247_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (cfg_mode(0) AND NOT cfg_mode(2) AND cfg_bank(20) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT cfg_mode(0) AND NOT cfg_mode(1) AND cfg_bank(20) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT cfg_mode(0) AND adr(7) AND cfg_bank(20) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT cfg_mode(1) AND cfg_bank(20) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT N247/N247_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (cfg_bank(20) AND
      NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 AND NOT N41/N41_D2)
      OR (NOT cfg_mode(5) AND cfg_bank(20) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (cfg_mode(4) AND cfg_bank(20) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (NOT cfg_mode(0) AND cfg_mode(3) AND cfg_bank(20) AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));
FDCPE_cfg_bank21: FDCPE port map (cfg_bank(21),cfg_bank_D(21),NOT phi2short,'0','0');
     cfg_bank_D(21) <= ((NOT cfg_mode(0) AND cfg_bank(21) AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (cfg_bank(21) AND NOT N247/N247_D2 AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (cfg_bank(21) AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 AND NOT N41/N41_D2)
      OR (data(7).PIN AND N247/N247_D2 AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2 AND N41/N41_D2)
      OR (data(0).PIN AND
      NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2 AND
      use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));
FDCPE_cfg_bank22: FDCPE port map (cfg_bank(22),cfg_bank_D(22),NOT phi2short,'0','0');
     cfg_bank_D(22) <= ((cfg_bank(22) AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (data(1).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));
FDCPE_cfg_bank23: FDCPE port map (cfg_bank(23),cfg_bank_D(23),NOT phi2short,'0','0');
     cfg_bank_D(23) <= ((cfg_bank(23) AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (data(2).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));
FDCPE_cfg_bank24: FDCPE port map (cfg_bank(24),cfg_bank_D(24),NOT phi2short,'0','0');
     cfg_bank_D(24) <= ((cfg_bank(24) AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (data(3).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));
FDCPE_cfg_bank25: FDCPE port map (cfg_bank(25),cfg_bank_D(25),NOT phi2short,'0','0');
     cfg_bank_D(25) <= ((cfg_bank(25) AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (data(4).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));
FDCPE_cfg_bank26: FDCPE port map (cfg_bank(26),cfg_bank_D(26),NOT phi2short,'0','0');
     cfg_bank_D(26) <= ((cfg_bank(26) AND
      NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (data(5).PIN AND reset_n_sync AND
      use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));
FDCPE_cfg_enable: FDCPE port map (cfg_enable,cfg_enable_D,NOT phi2short,'0','0');
     cfg_enable_D <= ((
      use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
      OR (cart_mem_adr(15).EXP)
      OR (NOT cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(3) AND
      cfg_enable AND NOT cctl_access_and0000/cctl_access_and0000_D2)
      OR (cfg_mode(2) AND NOT cfg_mode(3) AND cfg_enable AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT N247/N247_D2)
      OR (NOT cfg_mode(5) AND cfg_mode(3) AND cfg_enable AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND N219/N219_D2)
      OR (NOT cfg_mode(3) AND NOT cfg_mode(1) AND cfg_enable AND
      NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT N247/N247_D2)
      OR (NOT rw AND NOT adr(3) AND NOT adr(2) AND NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2)
      OR (EXP25_.EXP)
      OR (adr(0) AND cfg_enable AND
      cctl_access_and0000/cctl_access_and0000_D2)
      OR (rw AND cfg_mode(0) AND cfg_mode(5) AND cfg_enable)
      OR (rw AND cfg_mode(2) AND cfg_enable AND
      NOT use_cart_logic/N69/use_cart_logic/N69_D2)
      OR (rw AND cfg_mode(5) AND cfg_mode(3) AND cfg_enable)
      OR (NOT cfg_mode(3) AND cfg_mode(4) AND cfg_enable AND
      NOT cctl_access_and0000/cctl_access_and0000_D2)
      OR (cctl AND cfg_enable)
      OR (rw AND cfg_enable AND
      cctl_access_and0000/cctl_access_and0000_D2)
      OR (adr(3) AND cfg_enable AND
      cctl_access_and0000/cctl_access_and0000_D2)
      OR (adr(2) AND cfg_enable AND
      cctl_access_and0000/cctl_access_and0000_D2));
FTCPE_cfg_enable2: FTCPE port map (cfg_enable2,cfg_enable2_T,NOT phi2short,'0','0');
     cfg_enable2_T <= ((cfg_enable2 AND NOT reset_n_sync)
      OR (NOT rw AND NOT adr(3) AND adr(2) AND adr(0) AND cfg_enable2 AND
      NOT cctl AND NOT data(0).PIN AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2)
      OR (NOT rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT cfg_enable2 AND
      NOT cctl AND NOT adr(1) AND reset_n_sync AND
      cctl_access_and0000/cctl_access_and0000_D2)
      OR (NOT rw AND NOT adr(3) AND adr(2) AND NOT cfg_enable2 AND NOT cctl AND
      data(0).PIN AND NOT adr(1) AND reset_n_sync AND
      cctl_access_and0000/cctl_access_and0000_D2)
      OR (NOT rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT cfg_enable2 AND
      NOT cctl AND adr(1) AND reset_n_sync AND
      cctl_access_and0000/cctl_access_and0000_D2));
FDCPE_cfg_mode0: FDCPE port map (cfg_mode(0),cfg_mode_D(0),NOT phi2short,'0','0');
     cfg_mode_D(0) <= ((NOT cfg_mode(0) AND
      NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)
      OR (NOT data(0).PIN AND reset_n_sync AND
      use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2));
FDCPE_cfg_mode1: FDCPE port map (cfg_mode(1),cfg_mode_D(1),NOT phi2short,'0','0');
     cfg_mode_D(1) <= ((cfg_mode(1) AND
      NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)
      OR (data(1).PIN AND reset_n_sync AND
      use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2));
FDCPE_cfg_mode2: FDCPE port map (cfg_mode(2),cfg_mode_D(2),NOT phi2short,'0','0');
     cfg_mode_D(2) <= ((cfg_mode(2) AND
      NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)
      OR (data(2).PIN AND reset_n_sync AND
      use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2));
FDCPE_cfg_mode3: FDCPE port map (cfg_mode(3),cfg_mode_D(3),NOT phi2short,'0','0');
     cfg_mode_D(3) <= ((cfg_mode(3) AND
      NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)
      OR (data(3).PIN AND reset_n_sync AND
      use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2));
FDCPE_cfg_mode4: FDCPE port map (cfg_mode(4),cfg_mode_D(4),NOT phi2short,'0','0');
     cfg_mode_D(4) <= ((cfg_mode(4) AND
      NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)
      OR (data(4).PIN AND reset_n_sync AND
      use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2));
FDCPE_cfg_mode5: FDCPE port map (cfg_mode(5),cfg_mode_D(5),NOT phi2short,'0','0');
     cfg_mode_D(5) <= ((cfg_mode(5) AND
      NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)
      OR (data(5).PIN AND reset_n_sync AND
      use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2));
FDCPE_cfg_source_ram: FDCPE port map (cfg_source_ram,cfg_source_ram_D,NOT phi2short,'0','0');
     cfg_source_ram_D <= ((cfg_source_ram AND
      NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)
      OR (data(1).PIN AND reset_n_sync AND
      use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2));
FDCPE_cfg_source_ram2: FDCPE port map (cfg_source_ram2,cfg_source_ram2_D,NOT phi2short,'0','0');
     cfg_source_ram2_D <= ((cfg_source_ram2 AND
      NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)
      OR (data(3).PIN AND reset_n_sync AND
      use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2));
FDCPE_cfg_write_enable: FDCPE port map (cfg_write_enable,cfg_write_enable_D,NOT phi2short,'0','0');
     cfg_write_enable_D <= ((cfg_write_enable AND
      NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)
      OR (data(0).PIN AND reset_n_sync AND
      use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2));
FDCPE_cfg_write_enable2: FDCPE port map (cfg_write_enable2,cfg_write_enable2_D,NOT phi2short,'0','0');
     cfg_write_enable2_D <= ((cfg_write_enable2 AND
      NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)
      OR (data(2).PIN AND reset_n_sync AND
      use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2));
data_I(0) <= ((rw AND NOT adr(3) AND adr(2) AND adr(0) AND cfg_enable2 AND
      NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_mode(0) AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(13) AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT cctl AND NOT adr(1) AND
      cfg_bank(21) AND cctl_access_and0000/cctl_access_and0000_D2 AND
      data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
      cfg_bank(13) AND cctl_access_and0000/cctl_access_and0000_D2 AND
      data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND adr(2) AND adr(0) AND
      cfg_write_enable AND NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (ram_rom_data(0).PIN AND NOT data_or0000/data_or0000_D2)
      OR (rw AND NOT cctl AND cfg_bank(14) AND
      data_or0000/data_or0000_D2 AND N247/N247_D2)
      OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_bank2(21) AND
      NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND adr(1) AND
      cfg_enable AND cctl_access_and0000/cctl_access_and0000_D2 AND
      data_or0000/data_or0000_D2));
     data(0) <= data_I(0) when data_OE(0) = '1' else 'Z';
     data_OE(0) <= data_7_IOBUFE/data_7_IOBUFE_TRST;
data_I(1) <= ((rw AND NOT adr(3) AND adr(2) AND adr(0) AND cfg_source_ram AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_mode(1) AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_bank2(22) AND
      NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank(22) AND
      NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (ram_rom_data(1).PIN AND NOT data_or0000/data_or0000_D2)
      OR (rw AND NOT cctl AND cfg_bank(15) AND
      data_or0000/data_or0000_D2 AND N247/N247_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(14) AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
      cfg_bank(14) AND cctl_access_and0000/cctl_access_and0000_D2 AND
      data_or0000/data_or0000_D2));
     data(1) <= data_I(1) when data_OE(1) = '1' else 'Z';
     data_OE(1) <= data_7_IOBUFE/data_7_IOBUFE_TRST;
data_I(2) <= ((rw AND NOT adr(3) AND adr(2) AND adr(0) AND
      cfg_write_enable2 AND NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_mode(2) AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_bank2(23) AND
      NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank(23) AND
      NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (ram_rom_data(2).PIN AND NOT data_or0000/data_or0000_D2)
      OR (rw AND NOT cctl AND cfg_bank(16) AND
      data_or0000/data_or0000_D2 AND N247/N247_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(15) AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
      cfg_bank(15) AND cctl_access_and0000/cctl_access_and0000_D2 AND
      data_or0000/data_or0000_D2));
     data(2) <= data_I(2) when data_OE(2) = '1' else 'Z';
     data_OE(2) <= data_7_IOBUFE/data_7_IOBUFE_TRST;
data_I(3) <= ((rw AND NOT adr(3) AND adr(2) AND adr(0) AND
      cfg_source_ram2 AND NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_mode(3) AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_bank2(24) AND
      NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank(24) AND
      NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (ram_rom_data(3).PIN AND NOT data_or0000/data_or0000_D2)
      OR (rw AND NOT cctl AND cfg_bank(17) AND
      data_or0000/data_or0000_D2 AND N247/N247_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(16) AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
      cfg_bank(16) AND cctl_access_and0000/cctl_access_and0000_D2 AND
      data_or0000/data_or0000_D2));
     data(3) <= data_I(3) when data_OE(3) = '1' else 'Z';
     data_OE(3) <= data_7_IOBUFE/data_7_IOBUFE_TRST;
data_I(4) <= ((rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_mode(4) AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_bank2(25) AND
      NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank(25) AND
      NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (ram_rom_data(4).PIN AND NOT data_or0000/data_or0000_D2)
      OR (rw AND NOT cctl AND cfg_bank(18) AND
      data_or0000/data_or0000_D2 AND N247/N247_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(17) AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
      cfg_bank(17) AND cctl_access_and0000/cctl_access_and0000_D2 AND
      data_or0000/data_or0000_D2));
     data(4) <= data_I(4) when data_OE(4) = '1' else 'Z';
     data_OE(4) <= data_7_IOBUFE/data_7_IOBUFE_TRST;
data_I(5) <= ((rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_mode(5) AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_bank2(26) AND
      NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(18) AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank(26) AND
      NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (ram_rom_data(5).PIN AND NOT data_or0000/data_or0000_D2)
      OR (rw AND cfg_mode(0) AND NOT cctl AND cfg_bank(19) AND
      data_or0000/data_or0000_D2 AND N247/N247_D2)
      OR (rw AND NOT cfg_mode(0) AND sic_8xxx_enable AND NOT cctl AND
      data_or0000/data_or0000_D2 AND N247/N247_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
      cfg_bank(18) AND cctl_access_and0000/cctl_access_and0000_D2 AND
      data_or0000/data_or0000_D2));
     data(5) <= data_I(5) when data_OE(5) = '1' else 'Z';
     data_OE(5) <= data_7_IOBUFE/data_7_IOBUFE_TRST;
data_I(6) <= ((rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(19) AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (ram_rom_data(6).PIN AND NOT data_or0000/data_or0000_D2)
      OR (rw AND cfg_mode(0) AND NOT cctl AND cfg_bank(20) AND
      data_or0000/data_or0000_D2 AND N247/N247_D2)
      OR (rw AND NOT cfg_mode(0) AND NOT sic_axxx_enable AND NOT cctl AND
      data_or0000/data_or0000_D2 AND N247/N247_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
      cfg_bank(19) AND cctl_access_and0000/cctl_access_and0000_D2 AND
      data_or0000/data_or0000_D2));
     data(6) <= data_I(6) when data_OE(6) = '1' else 'Z';
     data_OE(6) <= data_7_IOBUFE/data_7_IOBUFE_TRST;
data_I(7) <= ((rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(20) AND
      NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
      OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
      cfg_bank(20) AND cctl_access_and0000/cctl_access_and0000_D2 AND
      data_or0000/data_or0000_D2)
      OR (ram_rom_data(7).PIN AND NOT data_or0000/data_or0000_D2)
      OR (rw AND cfg_mode(0) AND NOT cctl AND cfg_bank(21) AND
      data_or0000/data_or0000_D2 AND N247/N247_D2)
      OR (rw AND adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
      eeprom_so AND cctl_access_and0000/cctl_access_and0000_D2 AND
      data_or0000/data_or0000_D2));
     data(7) <= data_I(7) when data_OE(7) = '1' else 'Z';
     data_OE(7) <= data_7_IOBUFE/data_7_IOBUFE_TRST;
data_7_IOBUFE/data_7_IOBUFE_TRST <= ((rw AND phi2 AND data_or0000/data_or0000_D2)
      OR (rw AND phi2 AND
      do_access_mux0002/do_access_mux0002_D2));
data_or0000/data_or0000_D2 <= ((rw AND NOT adr(3) AND NOT cctl AND
      cctl_access_and0000/cctl_access_and0000_D2)
      OR (rw AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2)
      OR (rw AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(3) AND
      NOT cfg_mode(4) AND NOT cfg_mode(1) AND NOT cctl AND NOT adr(6) AND NOT adr(7) AND NOT adr(5)));
do_access_mux0002/do_access_mux0002_D2 <= ((NOT s4 AND rd4 AND $OpTx$INV$433)
      OR (NOT s5 AND rd5 AND $OpTx$INV$433 AND
      use_cart_logic/N23/use_cart_logic/N23_D2)
      OR (NOT s5 AND rd5 AND $OpTx$INV$433 AND
      use_cart_logic/N11/use_cart_logic/N11_D2));
FDCPE_eeprom_cs: FDCPE port map (eeprom_cs,eeprom_cs_D,NOT phi2short,'0','0');
     eeprom_cs_D <= ((NOT eeprom_cs AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (NOT data(1).PIN AND reset_n_sync AND
      use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2));
FDCPE_eeprom_sck: FDCPE port map (eeprom_sck,eeprom_sck_D,NOT phi2short,'0','0');
     eeprom_sck_D <= ((eeprom_sck AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (data(0).PIN AND reset_n_sync AND
      use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2));
FDCPE_eeprom_si: FDCPE port map (eeprom_si,eeprom_si_D,NOT phi2short,'0','0');
     eeprom_si_D <= ((NOT eeprom_si AND
      NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
      OR (NOT data(7).PIN AND reset_n_sync AND
      use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2));
FDCPE_mod_en: FDCPE port map (mod_en,mod_en_D,NOT phi2short,'0','0');
     mod_en_D <= ((mod_en AND reset_n_sync)
      OR (NOT rw AND adr(2) AND adr(0) AND NOT cctl AND adr(1) AND
      NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 AND cctl_access_and0000/cctl_access_and0000_D2));
FDCPE_oss_bank1: FDCPE port map (oss_bank(1),oss_bank_D(1),NOT phi2short,'0','0');
     oss_bank_D(1) <= ((oss_bank(1) AND
      NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2)
      OR (adr(0) AND reset_n_sync AND
      use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2));
ram_ce <= NOT (((cfg_source_ram AND
      do_access_mux0002/do_access_mux0002_D2 AND use_cart_logic/N23/use_cart_logic/N23_D2)
      OR (cfg_source_ram2 AND
      do_access_mux0002/do_access_mux0002_D2 AND use_cart_logic/N16/use_cart_logic/N16_D2)));
ram_rom_adr(0) <= adr(0);
ram_rom_adr(1) <= adr(1);
ram_rom_adr(2) <= adr(2);
ram_rom_adr(3) <= adr(3);
ram_rom_adr(4) <= adr(4);
ram_rom_adr(5) <= adr(5);
ram_rom_adr(6) <= adr(6);
ram_rom_adr(7) <= adr(7);
ram_rom_adr(8) <= adr(8);
ram_rom_adr(9) <= adr(9);
ram_rom_adr(10) <= adr(10);
ram_rom_adr(11) <= adr(11);
ram_rom_adr(12) <= ((cfg_mode(4) AND adr(12))
      OR (adr(12) AND NOT $OpTx$FX_DC$483)
      OR (NOT cfg_mode(4) AND use_cart_logic/oss_bank(0) AND
      NOT adr(12) AND $OpTx$FX_DC$483));
ram_rom_adr(13) <= ((cfg_mode(4) AND NOT s5 AND
      use_cart_logic/N23/use_cart_logic/N23_D2)
      OR (s4 AND cfg_mode(5) AND NOT cfg_mode(4) AND
      use_cart_logic/N11/use_cart_logic/N11_D2)
      OR (oss_bank(1) AND NOT adr(12) AND
      use_cart_logic/N23/use_cart_logic/N23_D2 AND $OpTx$FX_DC$483)
      OR (s4 AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND
      use_cart_logic/N23/use_cart_logic/N23_D2)
      OR (cfg_mode(4) AND cfg_bank(13))
      OR (cfg_bank2(13) AND
      use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (s4 AND cfg_bank(13) AND
      NOT use_cart_logic/N11/use_cart_logic/N11_D2)
      OR (NOT cfg_mode(5) AND cfg_bank(13) AND NOT $OpTx$FX_DC$483)
      OR (cfg_mode(1) AND cfg_bank(13) AND
      NOT use_cart_logic/N23/use_cart_logic/N23_D2));
ram_rom_adr(14) <= ((cfg_mode(4) AND NOT s5 AND
      use_cart_logic/N23/use_cart_logic/N23_D2)
      OR (cfg_bank2(14) AND
      use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_bank(14) AND
      NOT use_cart_logic/N16/use_cart_logic/N16_D2));
ram_rom_adr(15) <= ((cfg_bank2(15) AND
      use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_bank(15) AND
      NOT use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_mode(4) AND NOT s5 AND
      use_cart_logic/N23/use_cart_logic/N23_D2 AND NOT $OpTx$FX_DC$451));
ram_rom_adr(16) <= ((cfg_bank2(16) AND
      use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_bank(16) AND
      NOT use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_mode(2) AND cfg_mode(4) AND NOT s5 AND
      use_cart_logic/N23/use_cart_logic/N23_D2)
      OR (cfg_mode(4) AND cfg_mode(1) AND NOT s5 AND
      use_cart_logic/N23/use_cart_logic/N23_D2));
ram_rom_adr(17) <= ((cfg_bank2(17) AND
      use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_bank(17) AND
      NOT use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_mode(2) AND cfg_mode(4) AND NOT s5 AND
      use_cart_logic/N23/use_cart_logic/N23_D2)
      OR (cfg_mode(0) AND cfg_mode(4) AND cfg_mode(1) AND NOT s5 AND
      use_cart_logic/N23/use_cart_logic/N23_D2));
ram_rom_adr(18) <= ((cfg_bank2(18) AND
      use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_bank(18) AND
      NOT use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND
      NOT cfg_mode(1) AND NOT s5));
ram_rom_adr(19) <= ((cfg_bank2(19) AND
      use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_bank(19) AND
      NOT use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_mode(0) AND cfg_mode(2) AND cfg_mode(5) AND
      cfg_mode(4) AND NOT cfg_mode(1) AND NOT s5));
ram_rom_adr(20) <= ((cfg_bank2(20) AND
      use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_bank(20) AND
      NOT use_cart_logic/N16/use_cart_logic/N16_D2));
ram_rom_adr(21) <= ((cfg_bank2(21) AND
      use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_bank(21) AND
      NOT use_cart_logic/N16/use_cart_logic/N16_D2));
ram_rom_adr(22) <= ((cfg_bank2(22) AND
      use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_bank(22) AND
      NOT use_cart_logic/N16/use_cart_logic/N16_D2));
ram_rom_adr(23) <= ((cfg_bank2(23) AND
      use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_bank(23) AND
      NOT use_cart_logic/N16/use_cart_logic/N16_D2));
ram_rom_adr(24) <= ((cfg_bank(24) AND
      NOT use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_bank2(24) AND
      use_cart_logic/N16/use_cart_logic/N16_D2));
ram_rom_adr(25) <= ((cfg_bank2(25) AND
      use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_bank(25) AND
      NOT use_cart_logic/N16/use_cart_logic/N16_D2));
ram_rom_adr(26) <= ((cfg_bank2(26) AND
      use_cart_logic/N16/use_cart_logic/N16_D2)
      OR (cfg_bank(26) AND
      NOT use_cart_logic/N16/use_cart_logic/N16_D2));
ram_rom_data_I(0) <= data(0).PIN;
     ram_rom_data(0) <= ram_rom_data_I(0) when ram_rom_data_OE(0) = '1' else 'Z';
     ram_rom_data_OE(0) <= NOT rw;
ram_rom_data_I(1) <= data(1).PIN;
     ram_rom_data(1) <= ram_rom_data_I(1) when ram_rom_data_OE(1) = '1' else 'Z';
     ram_rom_data_OE(1) <= NOT rw;
ram_rom_data_I(2) <= data(2).PIN;
     ram_rom_data(2) <= ram_rom_data_I(2) when ram_rom_data_OE(2) = '1' else 'Z';
     ram_rom_data_OE(2) <= NOT rw;
ram_rom_data_I(3) <= data(3).PIN;
     ram_rom_data(3) <= ram_rom_data_I(3) when ram_rom_data_OE(3) = '1' else 'Z';
     ram_rom_data_OE(3) <= NOT rw;
ram_rom_data_I(4) <= data(4).PIN;
     ram_rom_data(4) <= ram_rom_data_I(4) when ram_rom_data_OE(4) = '1' else 'Z';
     ram_rom_data_OE(4) <= NOT rw;
ram_rom_data_I(5) <= data(5).PIN;
     ram_rom_data(5) <= ram_rom_data_I(5) when ram_rom_data_OE(5) = '1' else 'Z';
     ram_rom_data_OE(5) <= NOT rw;
ram_rom_data_I(6) <= data(6).PIN;
     ram_rom_data(6) <= ram_rom_data_I(6) when ram_rom_data_OE(6) = '1' else 'Z';
     ram_rom_data_OE(6) <= NOT rw;
ram_rom_data_I(7) <= data(7).PIN;
     ram_rom_data(7) <= ram_rom_data_I(7) when ram_rom_data_OE(7) = '1' else 'Z';
     ram_rom_data_OE(7) <= NOT rw;
ram_rom_oe <= NOT ((rw AND phi2));
ram_rom_we <= NOT ((NOT rw AND phi2short));
rd4 <= ((cfg_mode(0) AND cfg_mode(5) AND NOT cfg_mode(1) AND
      cfg_enable)
      OR (NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND
      cfg_enable)
      OR (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND
      sic_8xxx_enable AND cfg_enable)
      OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND
      NOT cfg_mode(3) AND NOT cfg_mode(4) AND NOT cfg_mode(1) AND cfg_enable2)
      OR (cfg_mode(5) AND cfg_mode(3) AND NOT cfg_mode(4) AND
      cfg_enable)
      OR (cfg_mode(5) AND cfg_mode(4) AND NOT cfg_mode(1) AND
      cfg_enable));
rd5 <= ((NOT cfg_mode(4) AND cfg_enable AND
      use_cart_logic/N11/use_cart_logic/N11_D2)
      OR (cfg_mode(0) AND cfg_mode(5) AND NOT cfg_mode(1) AND
      cfg_enable)
      OR (cfg_mode(5) AND cfg_mode(4) AND NOT cfg_mode(1) AND
      cfg_enable)
      OR (cfg_mode(5) AND NOT cfg_mode(1) AND sic_axxx_enable AND
      cfg_enable)
      OR (NOT cfg_mode(2) AND cfg_mode(5) AND cfg_enable));
FDCPE_reset_n_sync: FDCPE port map (reset_n_sync,reset_n_sync1,NOT phi2short,'0','0');
FDCPE_reset_n_sync1: FDCPE port map (reset_n_sync1,reset_n,NOT phi2short,'0','0');
rom_ce <= ((NOT do_access_mux0002/do_access_mux0002_D2)
      OR (cfg_source_ram AND
      use_cart_logic/N23/use_cart_logic/N23_D2)
      OR (cfg_source_ram2 AND
      use_cart_logic/N16/use_cart_logic/N16_D2));
FDCPE_rom_reset: FDCPE port map (rom_reset,'1',NOT phi2short,'0','0',reset_n_sync);
FDCPE_sic_8xxx_enable: FDCPE port map (sic_8xxx_enable,sic_8xxx_enable_D,NOT phi2short,'0','0');
     sic_8xxx_enable_D <= ((sic_8xxx_enable AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (data(5).PIN AND reset_n_sync AND
      use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2));
FDCPE_sic_axxx_enable: FDCPE port map (sic_axxx_enable,sic_axxx_enable_D,NOT phi2short,'0','0');
     sic_axxx_enable_D <= ((NOT sic_axxx_enable AND
      NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
      OR (data(6).PIN AND reset_n_sync AND
      use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2));
use_cart_logic/N11/use_cart_logic/N11_D2 <= ((NOT cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(5) AND
      NOT cfg_mode(1) AND oss_bank(1))
      OR (NOT cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(5) AND
      NOT cfg_mode(1) AND use_cart_logic/oss_bank(0))
      OR (cfg_mode(5) AND cfg_mode(3))
      OR (cfg_mode(3) AND NOT cfg_mode(1))
      OR (cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(3))
      OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(1)));
use_cart_logic/N16/use_cart_logic/N16_D2 <= (NOT s4 AND cfg_mode(5) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND
      $OpTx$FX_DC$451);
use_cart_logic/N23/use_cart_logic/N23_D2 <= ((cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(4) AND
      NOT cfg_mode(1))
      OR (NOT cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(4) AND
      NOT cfg_mode(1))
      OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(4) AND
      cfg_mode(1))
      OR (cfg_mode(5) AND cfg_mode(3) AND NOT cfg_mode(4))
      OR (cfg_mode(5) AND
      NOT use_cart_logic/N16/use_cart_logic/N16_D2 AND NOT $OpTx$FX_DC$444)
      OR (cfg_mode(3) AND NOT cfg_mode(4) AND NOT cfg_mode(1))
      OR (NOT cfg_mode(2) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND
      cfg_mode(1)));
use_cart_logic/N252/use_cart_logic/N252_D2 <= ((cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND
      adr(6) AND adr(7) AND NOT adr(5) AND adr(4))
      OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(1) AND
      adr(6) AND NOT adr(7) AND adr(5) AND adr(4))
      OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND
      adr(6) AND adr(7) AND adr(5) AND NOT adr(4)));
use_cart_logic/N69/use_cart_logic/N69_D2 <= ((cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(3) AND
      cfg_mode(1) AND NOT adr(7))
      OR (NOT cfg_mode(2) AND NOT cfg_mode(3) AND cfg_mode(1) AND
      NOT adr(7) AND $OpTx$FX_DC$457)
      OR (cfg_mode(0) AND cfg_mode(2) AND cfg_mode(3) AND
      NOT cfg_mode(1) AND NOT adr(7) AND $OpTx$FX_DC$457));
use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2 <= ((NOT reset_n_sync)
      OR (NOT rw AND NOT adr(3) AND adr(0) AND NOT cctl AND adr(1) AND
      NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 AND cctl_access_and0000/cctl_access_and0000_D2));
use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2 <= ((NOT reset_n_sync)
      OR (NOT rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT cctl AND
      cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2));
use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 <= ((NOT reset_n_sync)
      OR (NOT rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT cctl AND
      cctl_access_and0000/cctl_access_and0000_D2 AND
      NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));
use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2 <= ((NOT reset_n_sync)
      OR (NOT rw AND NOT adr(3) AND adr(2) AND NOT cctl AND adr(1) AND
      NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 AND cctl_access_and0000/cctl_access_and0000_D2));
use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 <= ((NOT reset_n_sync)
      OR (NOT rw AND NOT adr(3) AND adr(2) AND adr(0) AND NOT cctl AND adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2));
FDCPE_use_cart_logic/oss_bank0: FDCPE port map (use_cart_logic/oss_bank(0),use_cart_logic/oss_bank_D(0),NOT phi2short,'0','0');
     use_cart_logic/oss_bank_D(0) <= ((use_cart_logic/oss_bank(0) AND
      NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2)
      OR (NOT adr(3) AND reset_n_sync AND
      use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2));
use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 <= ((NOT reset_n_sync)
      OR (NOT cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(5) AND
      NOT cfg_mode(3) AND NOT cfg_mode(4) AND NOT cfg_mode(1) AND NOT cctl AND
      NOT cctl_access_and0000/cctl_access_and0000_D2));
use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2 <= ((NOT reset_n_sync)
      OR (NOT rw AND NOT cfg_mode(0) AND cfg_mode(2) AND cfg_mode(5) AND
      NOT cfg_mode(3) AND NOT cfg_mode(4) AND NOT cfg_mode(1) AND NOT cctl AND NOT adr(6) AND
      NOT adr(7) AND NOT adr(5)));
use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 <= ((NOT reset_n_sync)
      OR (NOT rw AND adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
      cctl_access_and0000/cctl_access_and0000_D2));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);