Timing Report

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Design Name	TheCart
Device, Speed (SpeedFile Version)	XC95144XL, -10 (3.0)
Date Created	Thu Dec 18 00:26:55 2025
Created By	Timing Report Generator: version P.20131013
Copyright	Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Performance Summary
Min. Clock Period	70.700 ns.
Max. Clock Frequency (fSYSTEM)	14.144 MHz.
Limited by Cycle Time for phi2short
Clock to Setup (tCYC)	70.700 ns.
Pad to Pad Delay (tPD)	77.000 ns.
Setup to Clock at the Pad (tSU)	67.200 ns.
Clock Pad to Output Pad Delay (tCO)	93.700 ns.

Timing Constraints

Constraint Name	Requirement (ns)	Delay (ns)	Paths
TS_phi_we	20.0	20.0	1
TS_phi_oe	20.0	20.0	1
TS_phi2short	560.0	70.7	227

Constraint: TS_phi_we

**Description: FROM:phi2short:TO:ram_rom_we:20.000nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)
phi2short to ram_rom_we	20.000	20.000	0.000

Constraint: TS_phi_oe

**Description: FROM:phi2:TO:ram_rom_oe:20.000nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)
phi2 to ram_rom_oe	20.000	20.000	0.000

Constraint: TS_phi2short

**Description: PERIOD:phi2short:560.000nS:HIGH:280.000nS**
Path	Requirement (ns)	Delay (ns)	Slack (ns)
mod_en.Q to cfg_bank<15>.D	560.000	70.700	489.300
mod_en.Q to cfg_bank<20>.D	560.000	70.700	489.300
mod_en.Q to cfg_bank<14>.D	560.000	70.300	489.700

Number of constraints not met: 0

Data Sheet Report

Maximum External Clock Speeds

Clock	fEXT (MHz)	Reason
phi2short	14.144	Limited by Cycle Time for phi2short

Setup/Hold Times for Clocks

**Setup/Hold Times for Clock phi2short**
Source Pad	Setup to clk (edge)	Hold to clk (edge)
adr<0>	54.000	0.000
adr<1>	54.000	0.000
adr<2>	54.000	0.000
adr<3>	54.000	0.000
adr<4>	67.200	0.000
adr<5>	67.200	0.000
adr<6>	67.200	0.000
adr<7>	67.200	0.000
cctl	54.000	0.000
data<0>	28.000	0.000
data<1>	28.000	0.000
data<2>	28.000	0.000
data<3>	28.000	0.000
data<4>	28.000	0.000
data<5>	28.000	0.000
data<6>	28.000	0.000
data<7>	28.000	0.000
reset_n	13.000	0.000
rw	54.000	0.000

Clock to Pad Timing

**Clock phi2short to Pad**
Destination Pad	Clock (edge) to Pad
data<0>	93.700
data<1>	93.700
data<2>	93.700
data<3>	93.700
data<4>	93.700
data<5>	93.700
data<6>	93.700
data<7>	93.700
ram_ce	90.500
rom_ce	89.500
ram_rom_adr<13>	64.100
ram_rom_adr<14>	64.100
ram_rom_adr<15>	64.100
ram_rom_adr<17>	64.100
ram_rom_adr<16>	63.100
ram_rom_adr<12>	50.900
ram_rom_adr<22>	50.900
ram_rom_adr<24>	50.900
ram_rom_adr<18>	49.900
ram_rom_adr<19>	49.900
ram_rom_adr<20>	49.900
ram_rom_adr<21>	49.900
ram_rom_adr<23>	49.900
ram_rom_adr<25>	49.900
ram_rom_adr<26>	49.900
rd5	38.700
rd4	24.500
eeprom_cs	10.300
eeprom_sck	10.300
eeprom_si	10.300
mod_en	10.300
rom_reset	10.300

Clock to Setup Times for Clocks

**Clock to Setup for clock phi2short**
Source	Destination	Delay
mod_en.Q	cfg_bank<15>.D	70.700
mod_en.Q	cfg_bank<20>.D	70.700
mod_en.Q	cfg_bank<14>.D	70.300
mod_en.Q	cfg_bank<16>.D	70.300
mod_en.Q	cfg_bank<17>.D	70.300
mod_en.Q	cfg_bank<18>.D	70.300
mod_en.Q	cfg_bank<21>.D	70.300
mod_en.Q	cfg_bank<22>.D	69.300
mod_en.Q	cfg_bank<23>.D	69.300
mod_en.Q	cfg_bank<24>.D	69.300
mod_en.Q	cfg_bank<25>.D	69.300
mod_en.Q	cfg_bank<26>.D	69.300
mod_en.Q	cfg_enable.D	69.300
mod_en.Q	cfg_bank2<21>.D	68.300
mod_en.Q	cfg_bank2<22>.D	68.300
mod_en.Q	cfg_bank2<23>.D	68.300
mod_en.Q	cfg_bank2<24>.D	68.300
mod_en.Q	cfg_bank2<25>.D	68.300
mod_en.Q	cfg_bank2<26>.D	68.300
reset_n_sync.Q	cfg_bank<15>.D	57.500
reset_n_sync.Q	cfg_bank<20>.D	57.500
mod_en.Q	cfg_bank<13>.D	57.100
reset_n_sync.Q	cfg_bank<14>.D	57.100
reset_n_sync.Q	cfg_bank<16>.D	57.100
reset_n_sync.Q	cfg_bank<17>.D	57.100
reset_n_sync.Q	cfg_bank<18>.D	57.100
reset_n_sync.Q	cfg_bank<21>.D	57.100
reset_n_sync.Q	cfg_bank<22>.D	56.100
reset_n_sync.Q	cfg_bank<23>.D	56.100
reset_n_sync.Q	cfg_bank<24>.D	56.100
reset_n_sync.Q	cfg_bank<25>.D	56.100
reset_n_sync.Q	cfg_bank<26>.D	56.100
reset_n_sync.Q	cfg_enable.D	56.100
mod_en.Q	cfg_bank2<13>.D	55.100
mod_en.Q	cfg_bank2<14>.D	55.100
mod_en.Q	cfg_bank2<15>.D	55.100
mod_en.Q	cfg_bank2<16>.D	55.100
mod_en.Q	cfg_bank2<17>.D	55.100
mod_en.Q	cfg_bank2<18>.D	55.100
mod_en.Q	cfg_bank2<19>.D	55.100
mod_en.Q	cfg_bank2<20>.D	55.100
mod_en.Q	cfg_mode<0>.D	55.100
mod_en.Q	cfg_mode<1>.D	55.100
mod_en.Q	cfg_mode<2>.D	55.100
mod_en.Q	cfg_mode<3>.D	55.100
mod_en.Q	cfg_mode<4>.D	55.100
mod_en.Q	cfg_mode<5>.D	55.100
reset_n_sync.Q	cfg_bank2<21>.D	55.100
reset_n_sync.Q	cfg_bank2<22>.D	55.100
reset_n_sync.Q	cfg_bank2<23>.D	55.100
reset_n_sync.Q	cfg_bank2<24>.D	55.100
reset_n_sync.Q	cfg_bank2<25>.D	55.100
reset_n_sync.Q	cfg_bank2<26>.D	55.100
cfg_mode<0>.Q	cfg_enable.D	44.300
cfg_mode<1>.Q	cfg_enable.D	44.300
cfg_mode<2>.Q	cfg_enable.D	44.300
cfg_mode<3>.Q	cfg_enable.D	44.300
cfg_mode<2>.Q	cfg_bank<13>.D	43.900
cfg_mode<0>.Q	cfg_bank<14>.D	42.900
cfg_mode<0>.Q	cfg_bank<15>.D	42.900
cfg_mode<1>.Q	cfg_bank<14>.D	42.900
cfg_mode<1>.Q	cfg_bank<15>.D	42.900
cfg_mode<1>.Q	cfg_bank<16>.D	42.900
cfg_mode<1>.Q	cfg_bank<17>.D	42.900
cfg_mode<2>.Q	cfg_bank<14>.D	42.900
cfg_mode<2>.Q	cfg_bank<15>.D	42.900
cfg_mode<2>.Q	cfg_bank<16>.D	42.900
cfg_mode<2>.Q	cfg_bank<17>.D	42.900
cfg_mode<3>.Q	cfg_bank<14>.D	42.900
cfg_mode<3>.Q	cfg_bank<15>.D	42.900
cfg_mode<3>.Q	cfg_bank<16>.D	42.900
cfg_mode<3>.Q	cfg_bank<17>.D	42.900
cfg_mode<4>.Q	cfg_bank<16>.D	42.900
cfg_mode<4>.Q	cfg_bank<17>.D	42.900
cfg_mode<5>.Q	cfg_bank<16>.D	42.900
cfg_mode<5>.Q	cfg_bank<17>.D	42.900
mod_en.Q	cfg_bank<19>.D	42.900
mod_en.Q	cfg_source_ram.D	41.900
mod_en.Q	cfg_source_ram2.D	41.900
mod_en.Q	cfg_write_enable.D	41.900
mod_en.Q	cfg_write_enable2.D	41.900
mod_en.Q	eeprom_cs.D	41.900
mod_en.Q	eeprom_sck.D	41.900
mod_en.Q	eeprom_si.D	41.900
mod_en.Q	mod_en.D	41.900
mod_en.Q	oss_bank<1>.D	41.900
mod_en.Q	use_cart_logic/oss_bank<0>.D	41.900
reset_n_sync.Q	cfg_bank2<13>.D	41.900
reset_n_sync.Q	cfg_bank2<14>.D	41.900
reset_n_sync.Q	cfg_bank2<15>.D	41.900
reset_n_sync.Q	cfg_bank2<16>.D	41.900
reset_n_sync.Q	cfg_bank2<17>.D	41.900
reset_n_sync.Q	cfg_bank2<18>.D	41.900
reset_n_sync.Q	cfg_bank2<19>.D	41.900
reset_n_sync.Q	cfg_bank2<20>.D	41.900
reset_n_sync.Q	cfg_mode<0>.D	41.900
reset_n_sync.Q	cfg_mode<1>.D	41.900
reset_n_sync.Q	cfg_mode<2>.D	41.900
reset_n_sync.Q	cfg_mode<3>.D	41.900
reset_n_sync.Q	cfg_mode<4>.D	41.900
reset_n_sync.Q	cfg_mode<5>.D	41.900
cfg_mode<5>.Q	cfg_enable.D	31.500
cfg_mode<0>.Q	cfg_bank<16>.D	31.100
cfg_mode<0>.Q	cfg_bank<17>.D	31.100
cfg_mode<4>.Q	cfg_enable.D	31.100
cfg_mode<0>.Q	cfg_bank<13>.D	30.700
cfg_mode<0>.Q	cfg_bank<18>.D	30.700
cfg_mode<0>.Q	cfg_bank<20>.D	30.700
cfg_mode<0>.Q	cfg_bank<21>.D	30.700
cfg_mode<1>.Q	cfg_bank<18>.D	30.700
cfg_mode<1>.Q	cfg_bank<20>.D	30.700
cfg_mode<1>.Q	cfg_bank<21>.D	30.700
cfg_mode<2>.Q	cfg_bank<18>.D	30.700
cfg_mode<2>.Q	cfg_bank<20>.D	30.700
cfg_mode<2>.Q	cfg_bank<21>.D	30.700
cfg_mode<3>.Q	cfg_bank<13>.D	30.700
cfg_mode<3>.Q	cfg_bank<18>.D	30.700
cfg_mode<3>.Q	cfg_bank<20>.D	30.700
cfg_mode<3>.Q	cfg_bank<21>.D	30.700
cfg_mode<4>.Q	cfg_bank<13>.D	30.700
cfg_mode<4>.Q	cfg_bank<18>.D	30.700
cfg_mode<4>.Q	cfg_bank<20>.D	30.700
cfg_mode<4>.Q	cfg_bank<21>.D	30.700
cfg_mode<5>.Q	cfg_bank<13>.D	30.700
cfg_mode<5>.Q	cfg_bank<18>.D	30.700
cfg_mode<5>.Q	cfg_bank<20>.D	30.700
cfg_mode<5>.Q	cfg_bank<21>.D	30.700
cfg_mode<1>.Q	cfg_bank<13>.D	30.100
cfg_mode<4>.Q	cfg_bank<15>.D	30.100
cfg_mode<5>.Q	cfg_bank<15>.D	30.100
reset_n_sync.Q	cfg_bank<13>.D	30.100
cfg_mode<0>.Q	cfg_bank<19>.D	29.700
cfg_mode<0>.Q	sic_8xxx_enable.D	29.700
cfg_mode<0>.Q	sic_axxx_enable.D	29.700
cfg_mode<1>.Q	cfg_bank<19>.D	29.700
cfg_mode<1>.Q	sic_8xxx_enable.D	29.700
cfg_mode<1>.Q	sic_axxx_enable.D	29.700
cfg_mode<2>.Q	cfg_bank<19>.D	29.700
cfg_mode<2>.Q	sic_8xxx_enable.D	29.700
cfg_mode<2>.Q	sic_axxx_enable.D	29.700
cfg_mode<3>.Q	cfg_bank<19>.D	29.700
cfg_mode<3>.Q	sic_8xxx_enable.D	29.700
cfg_mode<3>.Q	sic_axxx_enable.D	29.700
cfg_mode<4>.Q	cfg_bank<14>.D	29.700
cfg_mode<4>.Q	cfg_bank<19>.D	29.700
cfg_mode<4>.Q	sic_8xxx_enable.D	29.700
cfg_mode<4>.Q	sic_axxx_enable.D	29.700
cfg_mode<5>.Q	cfg_bank<14>.D	29.700
cfg_mode<5>.Q	cfg_bank<19>.D	29.700
cfg_mode<5>.Q	sic_8xxx_enable.D	29.700
cfg_mode<5>.Q	sic_axxx_enable.D	29.700
reset_n_sync.Q	cfg_bank<19>.D	29.700
reset_n_sync.Q	sic_8xxx_enable.D	29.700
reset_n_sync.Q	sic_axxx_enable.D	29.700
cfg_mode<0>.Q	oss_bank<1>.D	28.700
cfg_mode<0>.Q	use_cart_logic/oss_bank<0>.D	28.700
cfg_mode<1>.Q	oss_bank<1>.D	28.700
cfg_mode<1>.Q	use_cart_logic/oss_bank<0>.D	28.700
cfg_mode<2>.Q	oss_bank<1>.D	28.700
cfg_mode<2>.Q	use_cart_logic/oss_bank<0>.D	28.700
cfg_mode<3>.Q	oss_bank<1>.D	28.700
cfg_mode<3>.Q	use_cart_logic/oss_bank<0>.D	28.700
cfg_mode<4>.Q	oss_bank<1>.D	28.700
cfg_mode<4>.Q	use_cart_logic/oss_bank<0>.D	28.700
cfg_mode<5>.Q	oss_bank<1>.D	28.700
cfg_mode<5>.Q	use_cart_logic/oss_bank<0>.D	28.700
mod_en.Q	cfg_enable2.D	28.700
reset_n_sync.Q	cfg_source_ram.D	28.700
reset_n_sync.Q	cfg_source_ram2.D	28.700
reset_n_sync.Q	cfg_write_enable.D	28.700
reset_n_sync.Q	cfg_write_enable2.D	28.700
reset_n_sync.Q	eeprom_cs.D	28.700
reset_n_sync.Q	eeprom_sck.D	28.700
reset_n_sync.Q	eeprom_si.D	28.700
reset_n_sync.Q	mod_en.D	28.700
reset_n_sync.Q	oss_bank<1>.D	28.700
reset_n_sync.Q	use_cart_logic/oss_bank<0>.D	28.700
cfg_bank<13>.Q	cfg_bank<13>.D	16.900
cfg_bank<20>.Q	cfg_bank<20>.D	16.900
cfg_enable.Q	cfg_enable.D	16.900
cfg_bank<14>.Q	cfg_bank<14>.D	16.500
cfg_bank<15>.Q	cfg_bank<15>.D	16.500
cfg_bank<16>.Q	cfg_bank<16>.D	16.500
cfg_bank<17>.Q	cfg_bank<17>.D	16.500
cfg_bank<18>.Q	cfg_bank<18>.D	16.500
cfg_bank<19>.Q	cfg_bank<19>.D	16.500
cfg_bank<21>.Q	cfg_bank<21>.D	16.500
cfg_bank2<13>.Q	cfg_bank2<13>.D	15.500
cfg_bank2<14>.Q	cfg_bank2<14>.D	15.500
cfg_bank2<15>.Q	cfg_bank2<15>.D	15.500
cfg_bank2<16>.Q	cfg_bank2<16>.D	15.500
cfg_bank2<17>.Q	cfg_bank2<17>.D	15.500
cfg_bank2<18>.Q	cfg_bank2<18>.D	15.500
cfg_bank2<19>.Q	cfg_bank2<19>.D	15.500
cfg_bank2<20>.Q	cfg_bank2<20>.D	15.500
cfg_bank2<21>.Q	cfg_bank2<21>.D	15.500
cfg_bank2<22>.Q	cfg_bank2<22>.D	15.500
cfg_bank2<23>.Q	cfg_bank2<23>.D	15.500
cfg_bank2<24>.Q	cfg_bank2<24>.D	15.500
cfg_bank2<25>.Q	cfg_bank2<25>.D	15.500
cfg_bank2<26>.Q	cfg_bank2<26>.D	15.500
cfg_bank<22>.Q	cfg_bank<22>.D	15.500
cfg_bank<23>.Q	cfg_bank<23>.D	15.500
cfg_bank<24>.Q	cfg_bank<24>.D	15.500
cfg_bank<25>.Q	cfg_bank<25>.D	15.500
cfg_bank<26>.Q	cfg_bank<26>.D	15.500
cfg_enable2.Q	cfg_enable2.D	15.500
cfg_mode<0>.Q	cfg_mode<0>.D	15.500
cfg_mode<1>.Q	cfg_mode<1>.D	15.500
cfg_mode<2>.Q	cfg_mode<2>.D	15.500
cfg_mode<3>.Q	cfg_mode<3>.D	15.500
cfg_mode<4>.Q	cfg_mode<4>.D	15.500
cfg_mode<5>.Q	cfg_mode<5>.D	15.500
cfg_source_ram.Q	cfg_source_ram.D	15.500
cfg_source_ram2.Q	cfg_source_ram2.D	15.500
cfg_write_enable.Q	cfg_write_enable.D	15.500
cfg_write_enable2.Q	cfg_write_enable2.D	15.500
eeprom_cs.Q	eeprom_cs.D	15.500
eeprom_sck.Q	eeprom_sck.D	15.500
eeprom_si.Q	eeprom_si.D	15.500
oss_bank<1>.Q	oss_bank<1>.D	15.500
reset_n_sync.Q	cfg_enable2.D	15.500
reset_n_sync1.Q	reset_n_sync.D	15.500
sic_8xxx_enable.Q	sic_8xxx_enable.D	15.500
sic_axxx_enable.Q	sic_axxx_enable.D	15.500
use_cart_logic/oss_bank<0>.Q	use_cart_logic/oss_bank<0>.D	15.500
reset_n_sync.Q	rom_reset.CE	10.000

Pad to Pad List

Source Pad	Destination Pad	Delay
s4	data<0>	77.000
s4	data<1>	77.000
s4	data<2>	77.000
s4	data<3>	77.000
s4	data<4>	77.000
s4	data<5>	77.000
s4	data<6>	77.000
s4	data<7>	77.000
s4	ram_ce	73.800
s4	rom_ce	72.800
adr<4>	data<0>	50.600
adr<4>	data<1>	50.600
adr<4>	data<2>	50.600
adr<4>	data<3>	50.600
adr<4>	data<4>	50.600
adr<4>	data<5>	50.600
adr<4>	data<6>	50.600
adr<4>	data<7>	50.600
adr<5>	data<0>	50.600
adr<5>	data<1>	50.600
adr<5>	data<2>	50.600
adr<5>	data<3>	50.600
adr<5>	data<4>	50.600
adr<5>	data<5>	50.600
adr<5>	data<6>	50.600
adr<5>	data<7>	50.600
adr<6>	data<0>	50.600
adr<6>	data<1>	50.600
adr<6>	data<2>	50.600
adr<6>	data<3>	50.600
adr<6>	data<4>	50.600
adr<6>	data<5>	50.600
adr<6>	data<6>	50.600
adr<6>	data<7>	50.600
adr<7>	data<0>	50.600
adr<7>	data<1>	50.600
adr<7>	data<2>	50.600
adr<7>	data<3>	50.600
adr<7>	data<4>	50.600
adr<7>	data<5>	50.600
adr<7>	data<6>	50.600
adr<7>	data<7>	50.600
rw	data<0>	50.600
rw	data<1>	50.600
rw	data<2>	50.600
rw	data<3>	50.600
rw	data<4>	50.600
rw	data<5>	50.600
rw	data<6>	50.600
rw	data<7>	50.600
rw	ram_ce	47.400
s4	ram_rom_adr<13>	47.400
s4	ram_rom_adr<14>	47.400
s4	ram_rom_adr<15>	47.400
s4	ram_rom_adr<17>	47.400
rw	rom_ce	46.400
s4	ram_rom_adr<16>	46.400
adr<0>	data<0>	37.400
adr<0>	data<1>	37.400
adr<0>	data<2>	37.400
adr<0>	data<3>	37.400
adr<0>	data<4>	37.400
adr<0>	data<5>	37.400
adr<0>	data<6>	37.400
adr<0>	data<7>	37.400
adr<1>	data<0>	37.400
adr<1>	data<1>	37.400
adr<1>	data<2>	37.400
adr<1>	data<3>	37.400
adr<1>	data<4>	37.400
adr<1>	data<5>	37.400
adr<1>	data<6>	37.400
adr<1>	data<7>	37.400
adr<2>	data<0>	37.400
adr<2>	data<1>	37.400
adr<2>	data<2>	37.400
adr<2>	data<3>	37.400
adr<2>	data<4>	37.400
adr<2>	data<5>	37.400
adr<2>	data<6>	37.400
adr<2>	data<7>	37.400
adr<3>	data<0>	37.400
adr<3>	data<1>	37.400
adr<3>	data<2>	37.400
adr<3>	data<3>	37.400
adr<3>	data<4>	37.400
adr<3>	data<5>	37.400
adr<3>	data<6>	37.400
adr<3>	data<7>	37.400
cctl	data<0>	37.400
cctl	data<1>	37.400
cctl	data<2>	37.400
cctl	data<3>	37.400
cctl	data<4>	37.400
cctl	data<5>	37.400
cctl	data<6>	37.400
cctl	data<7>	37.400
s5	data<0>	37.400
s5	data<1>	37.400
s5	data<2>	37.400
s5	data<3>	37.400
s5	data<4>	37.400
s5	data<5>	37.400
s5	data<6>	37.400
s5	data<7>	37.400
s4	ram_rom_adr<22>	34.200
s4	ram_rom_adr<24>	34.200
s5	ram_ce	34.200
s4	ram_rom_adr<18>	33.200
s4	ram_rom_adr<19>	33.200
s4	ram_rom_adr<20>	33.200
s4	ram_rom_adr<21>	33.200
s4	ram_rom_adr<23>	33.200
s4	ram_rom_adr<25>	33.200
s4	ram_rom_adr<26>	33.200
s5	rom_ce	33.200
phi2	data<0>	24.200
phi2	data<1>	24.200
phi2	data<2>	24.200
phi2	data<3>	24.200
phi2	data<4>	24.200
phi2	data<5>	24.200
phi2	data<6>	24.200
phi2	data<7>	24.200
adr<0>	ram_rom_adr<0>	21.000
adr<12>	ram_rom_adr<13>	21.000
s5	ram_rom_adr<13>	21.000
s5	ram_rom_adr<14>	21.000
s5	ram_rom_adr<15>	21.000
s5	ram_rom_adr<17>	21.000
adr<10>	ram_rom_adr<10>	20.000
adr<11>	ram_rom_adr<11>	20.000
adr<12>	ram_rom_adr<12>	20.000
adr<1>	ram_rom_adr<1>	20.000
adr<2>	ram_rom_adr<2>	20.000
adr<3>	ram_rom_adr<3>	20.000
adr<4>	ram_rom_adr<4>	20.000
adr<5>	ram_rom_adr<5>	20.000
adr<6>	ram_rom_adr<6>	20.000
adr<7>	ram_rom_adr<7>	20.000
adr<8>	ram_rom_adr<8>	20.000
adr<9>	ram_rom_adr<9>	20.000
eeprom_so	data<7>	20.000
phi2	ram_rom_oe	20.000
phi2short	ram_rom_we	20.000
ram_rom_data<0>	data<0>	20.000
ram_rom_data<1>	data<1>	20.000
ram_rom_data<2>	data<2>	20.000
ram_rom_data<3>	data<3>	20.000
ram_rom_data<4>	data<4>	20.000
ram_rom_data<5>	data<5>	20.000
ram_rom_data<6>	data<6>	20.000
ram_rom_data<7>	data<7>	20.000
rw	ram_rom_oe	20.000
rw	ram_rom_we	20.000
s5	ram_rom_adr<16>	20.000
s5	ram_rom_adr<18>	20.000
s5	ram_rom_adr<19>	20.000
data<6>	ram_rom_data<6>	17.500
data<0>	ram_rom_data<0>	16.500
data<1>	ram_rom_data<1>	16.500
data<2>	ram_rom_data<2>	16.500
data<3>	ram_rom_data<3>	16.500
data<4>	ram_rom_data<4>	16.500
data<5>	ram_rom_data<5>	16.500
data<7>	ram_rom_data<7>	16.500
rw	ram_rom_data<0>	11.000
rw	ram_rom_data<1>	11.000
rw	ram_rom_data<2>	11.000
rw	ram_rom_data<3>	11.000
rw	ram_rom_data<4>	11.000
rw	ram_rom_data<5>	11.000
rw	ram_rom_data<6>	11.000
rw	ram_rom_data<7>	11.000

Number of paths analyzed: 229
Number of Timing errors: 0
Analysis Completed: Thu Dec 18 00:26:55 2025