cpldfit: version M.81d Xilinx Inc. Fitter Report Design Name: TurboFreezer Date: 11-18-2012, 2:43PM Device Used: XC95144XL-10-TQ100 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 137/144 ( 95%) 483 /720 ( 67%) 381/432 ( 88%) 72 /144 ( 50%) 59 /81 ( 73%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 16/18 50/54 85/90 11/11* FB2 18/18* 50/54 48/90 10/10* FB3 18/18* 50/54 72/90 9/10 FB4 18/18* 51/54 74/90 10/10* FB5 18/18* 46/54 43/90 6/10 FB6 13/18 51/54 64/90 9/10 FB7 18/18* 33/54 26/90 1/10 FB8 18/18* 50/54 71/90 3/10 ----- ----- ----- ----- 137/144 381/432 483/720 59/81 * - Resource is exhausted ** Global Control Resources ** Signal 'phi2' mapped onto global clock net GCK1. Signal 'phi2short' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 31 31 | I/O : 51 73 Output : 18 18 | GCK/IO : 3 3 Bidirectional : 8 8 | GTS/IO : 4 4 GCK : 2 2 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 59 59 ** Power Data ** There are 0 macrocells in high performance mode (MCHP). There are 137 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'TurboFreezer.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'mpd_in' based upon the LOC constraint 'P23'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'mpd_in_IBUF' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. ************************* Summary of Mapped Logic ************************ ** 26 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State d<0> 4 10 FB1_9 16 I/O I/O LOW SLOW d<1> 7 17 FB1_11 17 I/O I/O LOW SLOW d<2> 6 16 FB1_12 18 I/O I/O LOW SLOW d<3> 5 17 FB1_15 20 I/O I/O LOW SLOW d<4> 5 17 FB3_6 25 I/O I/O LOW SLOW d<5> 6 18 FB3_9 28 I/O I/O LOW SLOW d<6> 4 16 FB3_11 29 I/O I/O LOW SLOW d<7> 2 6 FB3_12 30 I/O I/O LOW SLOW ram_rom_a<15> 6 11 FB4_2 87 I/O O LOW SLOW ram_rom_a<16> 6 11 FB4_5 89 I/O O LOW SLOW ram_rom_a<17> 7 13 FB4_6 90 I/O O LOW SLOW ram_rom_a<18> 8 14 FB4_8 91 I/O O LOW SLOW ram_a<4> 8 16 FB4_9 92 I/O O LOW SLOW ram_a<5> 6 11 FB4_11 93 I/O O LOW SLOW ram_a<6> 4 9 FB4_12 94 I/O O LOW SLOW ram_a<7> 4 9 FB4_14 95 I/O O LOW SLOW ram1_ce 3 10 FB4_15 96 I/O O LOW SLOW rom1_ce 5 12 FB4_17 97 I/O O LOW SLOW ram_rom_we 1 2 FB6_6 77 I/O O LOW SLOW ram_rom_oe 1 2 FB6_8 78 I/O O LOW SLOW rom0_ce 4 10 FB6_9 79 I/O O LOW SLOW ram0_ce 7 16 FB6_12 81 I/O O LOW SLOW ram_rom_a<12> 12 17 FB6_14 82 I/O O LOW SLOW ram_rom_a<13> 8 18 FB6_15 85 I/O O LOW SLOW ram_rom_a<14> 6 11 FB6_17 86 I/O O LOW SLOW refresh 1 1 FB8_17 73 I/O O LOW SLOW ** 111 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State use_cartemu/cfg_enable 17 16 FB1_2 LOW RESET use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2 1 9 FB1_3 LOW use_cartemu/cfg_mode<0> 3 12 FB1_4 LOW RESET $OpTx$FX_DC$510 3 13 FB1_5 LOW use_cartemu/cfg_bank<5> 4 17 FB1_6 LOW RESET use_cartemu/cfg_bank<4> 4 17 FB1_7 LOW RESET use_cartemu/cfg_bank<3> 4 16 FB1_8 LOW RESET use_cartemu/cfg_bank<2> 4 16 FB1_10 LOW RESET use_cartemu/cfg_bank<1> 4 16 FB1_13 LOW RESET use_cartemu/cfg_bank<0> 4 16 FB1_14 LOW RESET dout_enable 7 16 FB1_16 LOW use_cartemu/cfg_write_enable 8 15 FB1_18 LOW RESET use_cartemu/N4/use_cartemu/N4_D2 1 8 FB2_1 LOW use_cartemu/usdx_bank<4> 2 6 FB2_2 LOW RESET use_cartemu/usdx_bank<3> 2 6 FB2_3 LOW RESET use_cartemu/usdx_bank<2> 2 6 FB2_4 LOW RESET use_cartemu/usdx_bank<1> 2 6 FB2_5 LOW RESET use_cartemu/cfg_sram_bank<4> 2 3 FB2_6 LOW RESET use_cartemu/cfg_sram_bank<3> 2 3 FB2_7 LOW RESET use_cartemu/cfg_sram_bank<2> 2 3 FB2_8 LOW RESET use_cartemu/cfg_sram_bank<1> 2 3 FB2_9 LOW RESET use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 2 4 FB2_10 LOW use_cartemu/usdx_ctl<1> 3 7 FB2_11 LOW RESET use_cartemu/usdx_ctl<0> 3 7 FB2_12 LOW RESET use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2 3 6 FB2_13 LOW use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2 3 6 FB2_14 LOW use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2 3 6 FB2_15 LOW $OpTx$FX_DC$577 3 6 FB2_16 LOW $OpTx$FX_DC$571 3 6 FB2_17 LOW use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 8 17 FB2_18 LOW $OpTx$FX_DC$508 1 3 FB3_1 LOW use_freezer/vector_a2 2 18 FB3_2 LOW RESET use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 2 3 FB3_3 LOW use_cartemu/N97/use_cartemu/N97_D2 2 10 FB3_4 LOW use_freezer/next_state_FSM_FFd3 3 18 FB3_5 LOW RESET use_freezer/next_state_FSM_FFd2 3 18 FB3_7 LOW RESET use_freezer/next_state_FSM_FFd1 3 6 FB3_8 LOW RESET use_cartemu/cfg_bank<6> 4 15 FB3_10 LOW RESET use_freezer/ram_bank_4 5 13 FB3_13 LOW RESET use_freezer/ram_bank_3 5 13 FB3_14 LOW RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State use_freezer/ram_bank_2 5 13 FB3_15 LOW RESET use_freezer/ram_bank_1 5 13 FB3_16 LOW RESET use_freezer/ram_bank_0 5 13 FB3_17 LOW RESET $OpTx$BIN_STEP$760 10 17 FB3_18 LOW $OpTx$FX_SC$591 1 8 FB4_1 LOW $OpTx$FX_SC$586 1 4 FB4_3 LOW $OpTx$FX_DC$521 1 6 FB4_4 LOW $OpTx$FX_DC$499 1 3 FB4_7 LOW use_freezer/N24/use_freezer/N24_D2 2 5 FB4_10 LOW freezer_mem_dout<5>/freezer_mem_dout<5>_D2 2 18 FB4_13 LOW $OpTx$FX_DC$538 3 8 FB4_16 LOW merged_out_dout_or0000/merged_out_dout_or0000_D2 6 13 FB4_18 LOW use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2 1 5 FB5_1 LOW $OpTx$FX_DC$580 1 7 FB5_2 LOW use_pia/pia_portb<4> 2 4 FB5_3 LOW RESET use_pia/pia_portb<3> 2 4 FB5_4 LOW RESET use_pia/pia_portb<2> 2 4 FB5_5 LOW RESET use_pia/pia_ddrb<7> 2 4 FB5_6 LOW RESET use_pia/pia_ddrb<6> 2 4 FB5_7 LOW RESET use_pia/pia_ddrb<5> 2 4 FB5_8 LOW RESET use_pia/pia_ddrb<4> 2 4 FB5_9 LOW RESET use_pia/pia_ddrb<3> 2 4 FB5_10 LOW RESET use_pia/pia_ddrb<2> 2 4 FB5_11 LOW RESET use_cartemu/usdx_bank<5> 2 6 FB5_12 LOW RESET use_cartemu/usdx_bank<0> 2 6 FB5_13 LOW RESET use_cartemu/oss_bank<1> 2 8 FB5_14 LOW RESET use_cartemu/oss_bank<0> 2 8 FB5_15 LOW RESET use_freezer/rom_bank_5 5 10 FB5_16 LOW RESET use_freezer/rom_bank_4 5 10 FB5_17 LOW RESET use_freezer/rom_bank_3 5 10 FB5_18 LOW RESET N0/N0_TRST 10 18 FB6_7 LOW use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2 7 12 FB6_10 LOW use_cartemu/N29/use_cartemu/N29_D2 3 6 FB6_11 LOW $OpTx$FX_DC$601 2 4 FB6_13 LOW use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 2 10 FB6_16 LOW $OpTx$FX_DC$522 1 2 FB6_18 LOW use_freezer/state<2> 1 1 FB7_1 LOW RESET use_freezer/state<1> 1 1 FB7_2 LOW RESET use_freezer/state<0> 1 1 FB7_3 LOW RESET reset_n_sync<3> 1 1 FB7_4 LOW RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State reset_n_sync<2> 1 1 FB7_5 LOW RESET reset_n_sync<1> 1 1 FB7_6 LOW RESET reset_n_sync<0> 1 1 FB7_7 LOW RESET ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2 1 5 FB7_8 LOW powerup_n 1 3 FB7_9 LOW RESET activate_n_sync<1> 1 1 FB7_10 LOW RESET activate_n_sync<0> 1 1 FB7_11 LOW RESET use_pia/pia_portb<7> 2 4 FB7_12 LOW RESET use_pia/pia_portb<6> 2 4 FB7_13 LOW RESET use_pia/pia_portb<5> 2 4 FB7_14 LOW RESET use_cartemu/cfg_sram_bank<5> 2 3 FB7_15 LOW RESET use_cartemu/cfg_sram_bank<0> 2 3 FB7_16 LOW RESET $OpTx$FX_DC$608 2 5 FB7_17 LOW $OpTx$FX_DC$540 3 5 FB7_18 LOW use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2 2 12 FB8_1 LOW use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2 2 12 FB8_2 LOW use_pia/pia_crb2 3 13 FB8_3 LOW RESET use_cartemu/cfg_usdx<1> 3 12 FB8_4 LOW RESET use_cartemu/cfg_usdx<0> 3 12 FB8_5 LOW RESET use_cartemu/cfg_source_ram 3 12 FB8_6 LOW RESET use_cartemu/cfg_mode<2> 3 12 FB8_7 LOW RESET use_cartemu/cfg_mode<1> 3 12 FB8_8 LOW RESET use_cartemu/cfg_sram_enable 4 11 FB8_9 LOW RESET use_cartemu/cfg_menu 4 13 FB8_10 LOW RESET use_freezer/use_status_as_ram_address<0> 5 12 FB8_11 LOW RESET use_freezer/rom_bank_2 5 10 FB8_12 LOW RESET use_freezer/rom_bank_1 5 10 FB8_13 LOW RESET use_freezer/rom_bank_0 5 10 FB8_14 LOW RESET use_cartemu/trig3_disable_atari 5 18 FB8_15 LOW $OpTx$INV$490 6 10 FB8_16 LOW use_cartemu/N50/use_cartemu/N50_D2 9 15 FB8_18 LOW ** 33 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use a<11> FB1_2 11 I/O I a<12> FB1_3 12 I/O I a<13> FB1_5 13 I/O I a<14> FB1_6 14 I/O I a<15> FB1_8 15 I/O I flash_we_n FB1_14 19 I/O I phi2 FB1_17 22 GCK/I/O GCK/I reset_n_in FB2_2 99 GSR/I/O I a<4> FB2_5 1 GTS/I/O I extsel_in FB2_6 2 GTS/I/O I a<5> FB2_8 3 GTS/I/O I a<6> FB2_9 4 GTS/I/O I a<7> FB2_11 6 I/O I cartemu_enable_n FB2_12 7 I/O I a<8> FB2_14 8 I/O I a<9> FB2_15 9 I/O I a<10> FB2_17 10 I/O I mpd_in FB3_2 23 GCK/I/O I ramdisk_enable_n FB3_5 24 I/O I phi2short FB3_8 27 GCK/I/O GCK/I rw FB3_15 33 I/O I dualpokey_n FB3_17 34 I/O I a<2> FB5_2 35 I/O I a<3> FB5_5 36 I/O I a<0> FB5_12 42 I/O I oldos_n FB5_14 43 I/O I activate_n_in FB5_15 46 I/O I irq_in FB5_17 49 I/O I nc_adr<3> FB6_2 74 I/O I nc_adr<4> FB6_5 76 I/O I a<1> FB7_2 50 I/O I nc_adr<1> FB8_14 71 I/O I nc_adr<2> FB8_15 72 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 50/4 Number of signals used by logic mapping into function block: 50 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/5 0 FB1_1 (b) (b) use_cartemu/cfg_enable 17 12<- 0 0 FB1_2 11 I/O I use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2 1 1<- /\5 0 FB1_3 12 I/O I use_cartemu/cfg_mode<0> 3 0 /\1 1 FB1_4 (b) (b) $OpTx$FX_DC$510 3 0 0 2 FB1_5 13 I/O I use_cartemu/cfg_bank<5> 4 0 0 1 FB1_6 14 I/O I use_cartemu/cfg_bank<4> 4 0 0 1 FB1_7 (b) (b) use_cartemu/cfg_bank<3> 4 0 \/1 0 FB1_8 15 I/O I d<0> 4 1<- \/2 0 FB1_9 16 I/O I/O use_cartemu/cfg_bank<2> 4 2<- \/3 0 FB1_10 (b) (b) d<1> 7 3<- \/1 0 FB1_11 17 I/O I/O d<2> 6 1<- 0 0 FB1_12 18 I/O I/O use_cartemu/cfg_bank<1> 4 0 \/1 0 FB1_13 (b) (b) use_cartemu/cfg_bank<0> 4 1<- \/2 0 FB1_14 19 I/O I d<3> 5 2<- \/2 0 FB1_15 20 I/O I/O dout_enable 7 2<- 0 0 FB1_16 (b) (b) (unused) 0 0 \/5 0 FB1_17 22 GCK/I/O GCK/I use_cartemu/cfg_write_enable 8 5<- \/2 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$499 18: dout_enable 35: use_cartemu/cfg_menu 2: $OpTx$FX_DC$508 19: freezer_mem_dout<5>/freezer_mem_dout<5>_D2 36: use_cartemu/cfg_mode<0> 3: $OpTx$FX_DC$510 20: merged_out_dout_or0000/merged_out_dout_or0000_D2 37: use_cartemu/cfg_mode<1> 4: d<5>.PIN 21: phi2 38: use_cartemu/cfg_mode<2> 5: d<4>.PIN 22: powerup_n 39: use_cartemu/cfg_source_ram 6: d<3>.PIN 23: reset_n_sync<1> 40: use_cartemu/cfg_sram_bank<1> 7: d<2>.PIN 24: rw 41: use_cartemu/cfg_sram_bank<2> 8: d<1>.PIN 25: use_cartemu/N50/use_cartemu/N50_D2 42: use_cartemu/cfg_sram_bank<3> 9: d<0>.PIN 26: use_cartemu/N97/use_cartemu/N97_D2 43: use_cartemu/cfg_usdx<0> 10: a<0> 27: use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 44: use_cartemu/cfg_usdx<1> 11: a<1> 28: use_cartemu/cfg_bank<0> 45: use_cartemu/cfg_write_enable 12: a<2> 29: use_cartemu/cfg_bank<1> 46: use_cartemu/trig3_disable_atari 13: a<3> 30: use_cartemu/cfg_bank<2> 47: use_cartemu/usdx_bank<1> 14: a<4> 31: use_cartemu/cfg_bank<3> 48: use_cartemu/usdx_bank<2> 15: a<5> 32: use_cartemu/cfg_bank<4> 49: use_cartemu/usdx_bank<3> 16: a<6> 33: use_cartemu/cfg_bank<5> 50: use_freezer/state<1> 17: a<7> 34: use_cartemu/cfg_enable Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs use_cartemu/cfg_enable XX......XXXXX...X....XXX..X......X.XXX...................... 16 use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2 X........XXXX...X.....XX..X................................. 9 use_cartemu/cfg_mode<0> X.......XXXXX...X....XXX..X........X........................ 12 $OpTx$FX_DC$510 X........XXXX..XX.....XX..X........XXX...................... 13 use_cartemu/cfg_bank<5> X.XX.....XXXX.XXX.....XX..X.....X..XXX...................... 17 use_cartemu/cfg_bank<4> X.X.X....XXXXX.XX.....XX..X....X...XXX...................... 17 use_cartemu/cfg_bank<3> X.X..X...XXXX..XX.....XX..X...X....XXX...................... 16 d<0> ............X...XXXX...XX.X..................X...X.......... 10 use_cartemu/cfg_bank<2> X.X...X..XXXX..XX.....XX..X..X.....XXX...................... 16 d<1> X........XXXX...XX.X...X.XX.X.......X.XX...X..X............. 17 d<2> X........XXXX...XX.X...X.XX..X....X..X..X......X............ 16 use_cartemu/cfg_bank<1> X.X....X.XXXX..XX.....XX..X.X......XXX...................... 16 use_cartemu/cfg_bank<0> X.X.....XXXXX..XX.....XX..XX.......XXX...................... 16 d<3> .........XXXXXXXXX.X...X..X...X..........XXX....X........... 17 dout_enable .........XXXXXXXX.XXX..X..X...............XX.X.............. 16 use_cartemu/cfg_write_enable XX......XXXXX...X.....XX..X........XXX......X............... 15 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 50/4 Number of signals used by logic mapping into function block: 50 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use use_cartemu/N4/use_cartemu/N4_D2 1 0 /\2 2 FB2_1 (b) (b) use_cartemu/usdx_bank<4> 2 0 0 3 FB2_2 99 GSR/I/O I use_cartemu/usdx_bank<3> 2 0 0 3 FB2_3 (b) (b) use_cartemu/usdx_bank<2> 2 0 0 3 FB2_4 (b) (b) use_cartemu/usdx_bank<1> 2 0 0 3 FB2_5 1 GTS/I/O I use_cartemu/cfg_sram_bank<4> 2 0 0 3 FB2_6 2 GTS/I/O I use_cartemu/cfg_sram_bank<3> 2 0 0 3 FB2_7 (b) (b) use_cartemu/cfg_sram_bank<2> 2 0 0 3 FB2_8 3 GTS/I/O I use_cartemu/cfg_sram_bank<1> 2 0 0 3 FB2_9 4 GTS/I/O I use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 2 0 0 3 FB2_10 (b) (b) use_cartemu/usdx_ctl<1> 3 0 0 2 FB2_11 6 I/O I use_cartemu/usdx_ctl<0> 3 0 0 2 FB2_12 7 I/O I use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2 3 0 0 2 FB2_13 (b) (b) use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2 3 0 0 2 FB2_14 8 I/O I use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2 3 0 0 2 FB2_15 9 I/O I $OpTx$FX_DC$577 3 0 0 2 FB2_16 (b) (b) $OpTx$FX_DC$571 3 0 \/1 1 FB2_17 10 I/O I use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 8 3<- 0 0 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$540 18: use_cartemu/N4/use_cartemu/N4_D2 35: use_cartemu/cfg_mode<2> 2: $OpTx$FX_DC$571 19: use_cartemu/N97/use_cartemu/N97_D2 36: use_cartemu/cfg_sram_bank<1> 3: $OpTx$FX_DC$577 20: use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 37: use_cartemu/cfg_sram_bank<2> 4: $OpTx$INV$490 21: use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2 38: use_cartemu/cfg_sram_bank<3> 5: d<7>.PIN 22: use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2 39: use_cartemu/cfg_sram_bank<4> 6: d<6>.PIN 23: use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2 40: use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2 7: d<4>.PIN 24: use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 41: use_cartemu/cfg_sram_enable 8: d<3>.PIN 25: use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2 42: use_cartemu/cfg_usdx<0> 9: d<2>.PIN 26: use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 43: use_cartemu/cfg_usdx<1> 10: d<1>.PIN 27: use_cartemu/cfg_bank<1> 44: use_cartemu/cfg_write_enable 11: a<13> 28: use_cartemu/cfg_bank<2> 45: use_cartemu/usdx_bank<1> 12: a<14> 29: use_cartemu/cfg_bank<3> 46: use_cartemu/usdx_bank<2> 13: a<15> 30: use_cartemu/cfg_bank<4> 47: use_cartemu/usdx_bank<3> 14: flash_we_n 31: use_cartemu/cfg_bank<6> 48: use_cartemu/usdx_bank<4> 15: powerup_n 32: use_cartemu/cfg_menu 49: use_cartemu/usdx_ctl<0> 16: reset_n_sync<1> 33: use_cartemu/cfg_mode<0> 50: use_cartemu/usdx_ctl<1> 17: rw 34: use_cartemu/cfg_mode<1> Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs use_cartemu/N4/use_cartemu/N4_D2 ..........XXX......X............XXX.....X................... 8 use_cartemu/usdx_bank<4> ......X........XX.X......X.....................X............ 6 use_cartemu/usdx_bank<3> .......X.......XX.X......X....................X............. 6 use_cartemu/usdx_bank<2> ........X......XX.X......X...................X.............. 6 use_cartemu/usdx_bank<1> .........X.....XX.X......X..................X............... 6 use_cartemu/cfg_sram_bank<4> ......X...............................XX.................... 3 use_cartemu/cfg_sram_bank<3> .......X.............................X.X.................... 3 use_cartemu/cfg_sram_bank<2> ........X...........................X..X.................... 3 use_cartemu/cfg_sram_bank<1> .........X.........................X...X.................... 3 use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 .......................X.................XX.....X........... 4 use_cartemu/usdx_ctl<1> ....X.........XXX.X......X.......................X.......... 7 use_cartemu/usdx_ctl<0> .....X........XXX.X......X......................X........... 7 use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2 .................X.....X.....X.X......X........X............ 6 use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2 .................X.....X....X..X.....X........X............. 6 use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2 .................X.....X...X...X....X........X.............. 6 $OpTx$FX_DC$577 .................X.....X......XX.........XX................. 6 $OpTx$FX_DC$571 .................X.....X..X....X...X........X............... 6 use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 XXXX.........X..XX.XXXX.X......XXXX........X................ 17 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 50/4 Number of signals used by logic mapping into function block: 50 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use $OpTx$FX_DC$508 1 1<- /\5 0 FB3_1 (b) (b) use_freezer/vector_a2 2 0 /\1 2 FB3_2 23 GCK/I/O I use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 2 0 0 3 FB3_3 (b) (b) use_cartemu/N97/use_cartemu/N97_D2 2 0 0 3 FB3_4 (b) (b) use_freezer/next_state_FSM_FFd3 3 0 0 2 FB3_5 24 I/O I d<4> 5 0 0 0 FB3_6 25 I/O I/O use_freezer/next_state_FSM_FFd2 3 0 0 2 FB3_7 (b) (b) use_freezer/next_state_FSM_FFd1 3 0 \/1 1 FB3_8 27 GCK/I/O GCK/I d<5> 6 1<- 0 0 FB3_9 28 I/O I/O use_cartemu/cfg_bank<6> 4 0 0 1 FB3_10 (b) (b) d<6> 4 0 0 1 FB3_11 29 I/O I/O d<7> 2 0 0 3 FB3_12 30 I/O I/O use_freezer/ram_bank_4 5 0 0 0 FB3_13 (b) (b) use_freezer/ram_bank_3 5 0 0 0 FB3_14 32 I/O (b) use_freezer/ram_bank_2 5 0 0 0 FB3_15 33 I/O I use_freezer/ram_bank_1 5 0 0 0 FB3_16 (b) (b) use_freezer/ram_bank_0 5 0 0 0 FB3_17 34 I/O I $OpTx$BIN_STEP$760 10 5<- 0 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$499 18: a<7> 35: use_cartemu/cfg_sram_bank<5> 2: $OpTx$FX_DC$508 19: activate_n_sync<1> 36: use_cartemu/cfg_usdx<0> 3: $OpTx$FX_DC$580 20: dout_enable 37: use_cartemu/cfg_usdx<1> 4: $OpTx$FX_SC$586 21: freezer_mem_dout<5>/freezer_mem_dout<5>_D2 38: use_cartemu/usdx_bank<4> 5: d<6>.PIN 22: merged_out_dout_or0000/merged_out_dout_or0000_D2 39: use_cartemu/usdx_bank<5> 6: a<0> 23: oldos_n 40: use_cartemu/usdx_ctl<0> 7: a<11> 24: reset_n_sync<1> 41: use_cartemu/usdx_ctl<1> 8: a<12> 25: rw 42: use_freezer/next_state_FSM_FFd1 9: a<13> 26: use_cartemu/N97/use_cartemu/N97_D2 43: use_freezer/next_state_FSM_FFd2 10: a<14> 27: use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 44: use_freezer/next_state_FSM_FFd3 11: a<15> 28: use_cartemu/cfg_bank<4> 45: use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2 12: a<1> 29: use_cartemu/cfg_bank<5> 46: use_freezer/ram_bank_0 13: a<2> 30: use_cartemu/cfg_bank<6> 47: use_freezer/ram_bank_1 14: a<3> 31: use_cartemu/cfg_mode<0> 48: use_freezer/ram_bank_2 15: a<4> 32: use_cartemu/cfg_mode<1> 49: use_freezer/ram_bank_3 16: a<5> 33: use_cartemu/cfg_mode<2> 50: use_freezer/ram_bank_4 17: a<6> 34: use_cartemu/cfg_sram_bank<4> Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs $OpTx$FX_DC$508 ..............XXX........................................... 3 use_freezer/vector_a2 ...X.XXXXXX.XXXXX.X....XX................XXX................ 18 use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 ...................................XX...X................... 3 use_cartemu/N97/use_cartemu/N97_D2 .....X.....XXXXXXX.................XX....................... 10 use_freezer/next_state_FSM_FFd3 ...X.XXXXXX..XXXX.X....XX................XXXX............... 18 d<4> .....X.....XXXXXXX.X.X..X.XX.....X.XXX...................... 17 use_freezer/next_state_FSM_FFd2 ..XX.XXXXXX..XXXX.X....XX................XXX................ 18 use_freezer/next_state_FSM_FFd1 ..X....................XX................XX.X............... 6 d<5> .....X.....XXXXXXX.XXX..X.X.X.....XXX.X..................... 18 use_cartemu/cfg_bank<6> X...XX.....XXX..XX.....XX.X..XXXX........................... 15 d<6> .....X.....XXXXXXX.X.X..X.X..X.....XX..X.................... 16 d<7> ...................X.X..XXX.............X................... 6 use_freezer/ram_bank_4 ...X..XXXXX...XXX........................XXX.....X.......... 13 use_freezer/ram_bank_3 ...X..XXXXX..X.XX........................XXX....X........... 13 use_freezer/ram_bank_2 ...X..XXXXX.X..XX........................XXX...X............ 13 use_freezer/ram_bank_1 ...X..XXXXXX...XX........................XXX..X............. 13 use_freezer/ram_bank_0 ...X.XXXXXX....XX........................XXX.X.............. 13 $OpTx$BIN_STEP$760 XX...X.X.XXXXX..XX....X..XX...XXX........................... 17 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 51/3 Number of signals used by logic mapping into function block: 51 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use $OpTx$FX_SC$591 1 0 \/1 3 FB4_1 (b) (b) ram_rom_a<15> 6 1<- 0 0 FB4_2 87 I/O O $OpTx$FX_SC$586 1 0 0 4 FB4_3 (b) (b) $OpTx$FX_DC$521 1 0 \/3 1 FB4_4 (b) (b) ram_rom_a<16> 6 3<- \/2 0 FB4_5 89 I/O O ram_rom_a<17> 7 2<- 0 0 FB4_6 90 I/O O $OpTx$FX_DC$499 1 0 \/3 1 FB4_7 (b) (b) ram_rom_a<18> 8 3<- 0 0 FB4_8 91 I/O O ram_a<4> 8 3<- 0 0 FB4_9 92 I/O O use_freezer/N24/use_freezer/N24_D2 2 0 /\3 0 FB4_10 (b) (b) ram_a<5> 6 1<- 0 0 FB4_11 93 I/O O ram_a<6> 4 0 /\1 0 FB4_12 94 I/O O freezer_mem_dout<5>/freezer_mem_dout<5>_D2 2 0 0 3 FB4_13 (b) (b) ram_a<7> 4 0 0 1 FB4_14 95 I/O O ram1_ce 3 0 0 2 FB4_15 96 I/O O $OpTx$FX_DC$538 3 0 \/1 1 FB4_16 (b) (b) rom1_ce 5 1<- \/1 0 FB4_17 97 I/O O merged_out_dout_or0000/merged_out_dout_or0000_D2 6 1<- 0 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$538 18: a<8> 35: use_freezer/rom_bank_2 2: $OpTx$FX_DC$540 19: a<9> 36: use_freezer/rom_bank_3 3: $OpTx$FX_DC$577 20: dualpokey_n 37: use_freezer/rom_bank_4 4: $OpTx$FX_SC$591 21: freezer_mem_dout<5>/freezer_mem_dout<5>_D2 38: use_freezer/rom_bank_5 5: $OpTx$INV$490 22: merged_out_dout_or0000/merged_out_dout_or0000_D2 39: use_freezer/state<0> 6: a<0> 23: oldos_n 40: use_freezer/state<1> 7: a<10> 24: phi2 41: use_freezer/state<2> 8: a<11> 25: ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2 42: use_freezer/use_status_as_ram_address<0> 9: a<12> 26: rw 43: use_freezer/vector_a2 10: a<13> 27: use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2 44: use_pia/pia_ddrb<3> 11: a<14> 28: use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2 45: use_pia/pia_ddrb<5> 12: a<15> 29: use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2 46: use_pia/pia_ddrb<6> 13: a<3> 30: use_cartemu/cfg_menu 47: use_pia/pia_ddrb<7> 14: a<4> 31: use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 48: use_pia/pia_portb<3> 15: a<5> 32: use_freezer/N24/use_freezer/N24_D2 49: use_pia/pia_portb<5> 16: a<6> 33: use_freezer/ram_bank_3 50: use_pia/pia_portb<6> 17: a<7> 34: use_freezer/ram_bank_4 51: use_pia/pia_portb<7> Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs $OpTx$FX_SC$591 .......XXXXX.............X.............XX................... 8 ram_rom_a<15> X........X...........X..X.X...XXX.X........X...X............ 11 $OpTx$FX_SC$586 ......X.........XXX......................................... 4 $OpTx$FX_DC$521 .......XXXXX....X........................................... 6 ram_rom_a<16> X........X...........X..X..X..XX.X.X........X...X........... 11 ram_rom_a<17> ...X.....XXX.........XX.X...X.XX....X........X...X.......... 13 $OpTx$FX_DC$499 .............XXX............................................ 3 ram_rom_a<18> .X.X.....XXX.........XX.X....XXX.....X........X...X......... 14 ram_a<4> ...X..X..XXX.X...XXX.XX.X.....XX.........XX................. 16 use_freezer/N24/use_freezer/N24_D2 ..........XX..........................XXX................... 5 ram_a<5> .........XXX..X....X.XX.X.....XX.........X.................. 11 ram_a<6> .........XXX...X.....XX.X.....XX............................ 9 freezer_mem_dout<5>/freezer_mem_dout<5>_D2 .....XXXXXXXXXXXXXX......X............XXX................... 18 ram_a<7> .........XXX....X....XX.X.....XX............................ 9 ram1_ce ..X.X....XXX.........XXXX.....X............................. 10 $OpTx$FX_DC$538 ...X....XXXX.........XX........X............................ 8 rom1_ce ..X.X....XXX.........XXXXX....XX............................ 12 merged_out_dout_or0000/merged_out_dout_or0000_D2 ......XXXXXX.....XX.X....X............XXX................... 13 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 46/8 Number of signals used by logic mapping into function block: 46 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2 1 0 0 4 FB5_1 (b) (b) $OpTx$FX_DC$580 1 0 0 4 FB5_2 35 I/O I use_pia/pia_portb<4> 2 0 0 3 FB5_3 (b) (b) use_pia/pia_portb<3> 2 0 0 3 FB5_4 (b) (b) use_pia/pia_portb<2> 2 0 0 3 FB5_5 36 I/O I use_pia/pia_ddrb<7> 2 0 0 3 FB5_6 37 I/O (b) use_pia/pia_ddrb<6> 2 0 0 3 FB5_7 (b) (b) use_pia/pia_ddrb<5> 2 0 0 3 FB5_8 39 I/O (b) use_pia/pia_ddrb<4> 2 0 0 3 FB5_9 40 I/O (b) use_pia/pia_ddrb<3> 2 0 0 3 FB5_10 (b) (b) use_pia/pia_ddrb<2> 2 0 0 3 FB5_11 41 I/O (b) use_cartemu/usdx_bank<5> 2 0 0 3 FB5_12 42 I/O I use_cartemu/usdx_bank<0> 2 0 0 3 FB5_13 (b) (b) use_cartemu/oss_bank<1> 2 0 0 3 FB5_14 43 I/O I use_cartemu/oss_bank<0> 2 0 0 3 FB5_15 46 I/O I use_freezer/rom_bank_5 5 0 0 0 FB5_16 (b) (b) use_freezer/rom_bank_4 5 0 0 0 FB5_17 49 I/O I use_freezer/rom_bank_3 5 0 0 0 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$508 17: a<7> 32: use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2 2: $OpTx$FX_DC$521 18: a<8> 33: use_freezer/rom_bank_3 3: $OpTx$FX_DC$522 19: a<9> 34: use_freezer/rom_bank_4 4: d<7>.PIN 20: reset_n_sync<1> 35: use_freezer/rom_bank_5 5: d<6>.PIN 21: rw 36: use_pia/pia_ddrb<2> 6: d<5>.PIN 22: use_cartemu/N97/use_cartemu/N97_D2 37: use_pia/pia_ddrb<3> 7: d<4>.PIN 23: use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 38: use_pia/pia_ddrb<4> 8: d<3>.PIN 24: use_cartemu/cfg_mode<0> 39: use_pia/pia_ddrb<5> 9: d<2>.PIN 25: use_cartemu/oss_bank<0> 40: use_pia/pia_ddrb<6> 10: d<0>.PIN 26: use_cartemu/oss_bank<1> 41: use_pia/pia_ddrb<7> 11: a<0> 27: use_cartemu/usdx_bank<0> 42: use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2 12: a<10> 28: use_cartemu/usdx_bank<5> 43: use_pia/pia_portb<2> 13: a<3> 29: use_freezer/next_state_FSM_FFd1 44: use_pia/pia_portb<3> 14: a<4> 30: use_freezer/next_state_FSM_FFd2 45: use_pia/pia_portb<4> 15: a<5> 31: use_freezer/next_state_FSM_FFd3 46: use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2 16: a<6> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2 XX.........X.....XX............................... 5 $OpTx$FX_DC$580 .X.........X.X.X.XX............X.................. 7 use_pia/pia_portb<4> ......X............X........................XX.... 4 use_pia/pia_portb<3> .......X...........X.......................X.X.... 4 use_pia/pia_portb<2> ........X..........X......................X..X.... 4 use_pia/pia_ddrb<7> ...X...............X....................XX........ 4 use_pia/pia_ddrb<6> ....X..............X...................X.X........ 4 use_pia/pia_ddrb<5> .....X.............X..................X..X........ 4 use_pia/pia_ddrb<4> ......X............X.................X...X........ 4 use_pia/pia_ddrb<3> .......X...........X................X....X........ 4 use_pia/pia_ddrb<2> ........X..........X...............X.....X........ 4 use_cartemu/usdx_bank<5> .....X.............XXXX....X...................... 6 use_cartemu/usdx_bank<0> .........X.........XXXX...X....................... 6 use_cartemu/oss_bank<1> X.X.......X.....X..X..XX.X........................ 8 use_cartemu/oss_bank<0> X.X.........X...X..X..XXX......................... 8 use_freezer/rom_bank_5 .X.........X..XX.XX.........XXX...X............... 10 use_freezer/rom_bank_4 .X.........X.X.X.XX.........XXX..X................ 10 use_freezer/rom_bank_3 .X.........XX..X.XX.........XXX.X................. 10 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 51/3 Number of signals used by logic mapping into function block: 51 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB6_1 (b) (unused) 0 0 0 5 FB6_2 74 I/O I (unused) 0 0 0 5 FB6_3 (b) (unused) 0 0 0 5 FB6_4 (b) (unused) 0 0 \/1 4 FB6_5 76 I/O I ram_rom_we 1 1<- \/5 0 FB6_6 77 I/O O N0/N0_TRST 10 5<- 0 0 FB6_7 (b) (b) ram_rom_oe 1 0 \/3 1 FB6_8 78 I/O O rom0_ce 4 3<- \/4 0 FB6_9 79 I/O O use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2 7 4<- \/2 0 FB6_10 (b) (b) use_cartemu/N29/use_cartemu/N29_D2 3 2<- \/4 0 FB6_11 80 I/O (b) ram0_ce 7 4<- \/2 0 FB6_12 81 I/O O $OpTx$FX_DC$601 2 2<- \/5 0 FB6_13 (b) (b) ram_rom_a<12> 12 7<- 0 0 FB6_14 82 I/O O ram_rom_a<13> 8 5<- /\2 0 FB6_15 85 I/O O use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 2 2<- /\5 0 FB6_16 (b) (b) ram_rom_a<14> 6 3<- /\2 0 FB6_17 86 I/O O $OpTx$FX_DC$522 1 0 /\3 1 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$BIN_STEP$760 18: flash_we_n 35: use_cartemu/cfg_mode<1> 2: $OpTx$FX_DC$522 19: freezer_mem_dout<5>/freezer_mem_dout<5>_D2 36: use_cartemu/cfg_mode<2> 3: $OpTx$FX_DC$538 20: merged_out_dout_or0000/merged_out_dout_or0000_D2 37: use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 4: $OpTx$FX_DC$571 21: oldos_n 38: use_cartemu/oss_bank<0> 5: $OpTx$FX_DC$577 22: phi2 39: use_cartemu/oss_bank<1> 6: $OpTx$FX_DC$608 23: phi2short 40: use_cartemu/trig3_disable_atari 7: $OpTx$FX_SC$591 24: ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2 41: use_freezer/N24/use_freezer/N24_D2 8: $OpTx$INV$490 25: rw 42: use_freezer/ram_bank_0 9: a<10> 26: use_cartemu/N29/use_cartemu/N29_D2 43: use_freezer/ram_bank_1 10: a<11> 27: use_cartemu/N4/use_cartemu/N4_D2 44: use_freezer/ram_bank_2 11: a<12> 28: use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 45: use_freezer/rom_bank_0 12: a<13> 29: use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 46: use_freezer/rom_bank_1 13: a<14> 30: use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2 47: use_freezer/state<0> 14: a<15> 31: use_cartemu/cfg_bank<0> 48: use_freezer/state<1> 15: a<8> 32: use_cartemu/cfg_enable 49: use_freezer/state<2> 16: a<9> 33: use_cartemu/cfg_menu 50: use_pia/pia_ddrb<2> 17: cartemu_enable_n 34: use_cartemu/cfg_mode<0> 51: use_pia/pia_portb<2> Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs ram_rom_we ......................X.X................................... 2 N0/N0_TRST X.......XXXXXXXX..XXX..X.....X.........X......XXX........... 18 ram_rom_oe .....................X..X................................... 2 rom0_ce ....X..X...XXX.....XXX.X............X....................... 10 use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2 ...........XXX...........XXXX..XXXXX........................ 12 use_cartemu/N29/use_cartemu/N29_D2 .X........................XX.....X...XX..................... 6 ram0_ce ....X..X.XXXXX.....XXX.XX...........X.........XXX........... 16 $OpTx$FX_DC$601 ..................................XX.XX..................... 4 ram_rom_a<12> .X....X...XXXX.....XX..X...X....XX..XXX.XX.................. 17 ram_rom_a<13> .XX..X....XX.......X...X.X.XX.X.XX..X.X.X.X.X............... 18 use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 ........XXXXXXXXXX.......................................... 10 ram_rom_a<14> ..XX.......X.......X...X............X...X..X.X...XX......... 11 $OpTx$FX_DC$522 ..................................XX........................ 2 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 33/21 Number of signals used by logic mapping into function block: 33 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use use_freezer/state<2> 1 0 0 4 FB7_1 (b) (b) use_freezer/state<1> 1 0 0 4 FB7_2 50 I/O I use_freezer/state<0> 1 0 0 4 FB7_3 (b) (b) reset_n_sync<3> 1 0 0 4 FB7_4 (b) (b) reset_n_sync<2> 1 0 0 4 FB7_5 52 I/O (b) reset_n_sync<1> 1 0 0 4 FB7_6 53 I/O (b) reset_n_sync<0> 1 0 0 4 FB7_7 (b) (b) ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2 1 0 0 4 FB7_8 54 I/O (b) powerup_n 1 0 0 4 FB7_9 55 I/O (b) activate_n_sync<1> 1 0 0 4 FB7_10 (b) (b) activate_n_sync<0> 1 0 0 4 FB7_11 56 I/O (b) use_pia/pia_portb<7> 2 0 0 3 FB7_12 58 I/O (b) use_pia/pia_portb<6> 2 0 0 3 FB7_13 (b) (b) use_pia/pia_portb<5> 2 0 0 3 FB7_14 59 I/O (b) use_cartemu/cfg_sram_bank<5> 2 0 0 3 FB7_15 60 I/O (b) use_cartemu/cfg_sram_bank<0> 2 0 0 3 FB7_16 (b) (b) $OpTx$FX_DC$608 2 0 0 3 FB7_17 61 I/O (b) $OpTx$FX_DC$540 3 0 0 2 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: d<7>.PIN 12: reset_n_sync<0> 23: use_cartemu/usdx_bank<0> 2: d<6>.PIN 13: reset_n_sync<1> 24: use_cartemu/usdx_bank<5> 3: d<5>.PIN 14: reset_n_sync<2> 25: use_freezer/next_state_FSM_FFd1 4: d<0>.PIN 15: reset_n_sync<3> 26: use_freezer/next_state_FSM_FFd2 5: a<14> 16: use_cartemu/N29/use_cartemu/N29_D2 27: use_freezer/next_state_FSM_FFd3 6: a<15> 17: use_cartemu/N4/use_cartemu/N4_D2 28: use_pia/pia_ddrb<4> 7: activate_n_in 18: use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 29: use_pia/pia_portb<4> 8: activate_n_sync<0> 19: use_cartemu/cfg_bank<5> 30: use_pia/pia_portb<5> 9: powerup_n 20: use_cartemu/cfg_sram_bank<0> 31: use_pia/pia_portb<6> 10: ramdisk_enable_n 21: use_cartemu/cfg_sram_bank<5> 32: use_pia/pia_portb<7> 11: reset_n_in 22: use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2 33: use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs use_freezer/state<2> ........................X............... 1 use_freezer/state<1> .........................X.............. 1 use_freezer/state<0> ..........................X............. 1 reset_n_sync<3> .............X.......................... 1 reset_n_sync<2> ............X........................... 1 reset_n_sync<1> ...........X............................ 1 reset_n_sync<0> ..........X............................. 1 ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2 ....XX...X.................XX........... 5 powerup_n ........X....XX......................... 3 activate_n_sync<1> .......X................................ 1 activate_n_sync<0> ......X................................. 1 use_pia/pia_portb<7> X...........X..................XX....... 4 use_pia/pia_portb<6> .X..........X.................X.X....... 4 use_pia/pia_portb<5> ..X.........X................X..X....... 4 use_cartemu/cfg_sram_bank<5> ..X.................XX.................. 3 use_cartemu/cfg_sram_bank<0> ...X...............X.X.................. 3 $OpTx$FX_DC$608 ...............XXX.X..X................. 5 $OpTx$FX_DC$540 ................XXX.X..X................ 5 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 50/4 Number of signals used by logic mapping into function block: 50 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2 2 1<- /\4 0 FB8_1 (b) (b) use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2 2 0 /\1 2 FB8_2 63 I/O (b) use_pia/pia_crb2 3 0 0 2 FB8_3 (b) (b) use_cartemu/cfg_usdx<1> 3 0 0 2 FB8_4 (b) (b) use_cartemu/cfg_usdx<0> 3 0 0 2 FB8_5 64 I/O (b) use_cartemu/cfg_source_ram 3 0 0 2 FB8_6 65 I/O (b) use_cartemu/cfg_mode<2> 3 0 0 2 FB8_7 (b) (b) use_cartemu/cfg_mode<1> 3 0 0 2 FB8_8 66 I/O (b) use_cartemu/cfg_sram_enable 4 0 0 1 FB8_9 67 I/O (b) use_cartemu/cfg_menu 4 0 0 1 FB8_10 (b) (b) use_freezer/use_status_as_ram_address<0> 5 0 0 0 FB8_11 68 I/O (b) use_freezer/rom_bank_2 5 0 0 0 FB8_12 70 I/O (b) use_freezer/rom_bank_1 5 0 0 0 FB8_13 (b) (b) use_freezer/rom_bank_0 5 0 0 0 FB8_14 71 I/O I use_cartemu/trig3_disable_atari 5 0 0 0 FB8_15 72 I/O I $OpTx$INV$490 6 1<- 0 0 FB8_16 (b) (b) refresh 1 0 /\1 3 FB8_17 73 I/O O use_cartemu/N50/use_cartemu/N50_D2 9 4<- 0 0 FB8_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$499 18: a<8> 35: use_cartemu/cfg_sram_bank<0> 2: $OpTx$FX_DC$508 19: a<9> 36: use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2 3: $OpTx$FX_DC$521 20: cartemu_enable_n 37: use_cartemu/cfg_sram_enable 4: $OpTx$FX_DC$601 21: powerup_n 38: use_cartemu/cfg_usdx<0> 5: N0/N0_TRST 22: reset_n_sync<1> 39: use_cartemu/cfg_usdx<1> 6: d<2>.PIN 23: rw 40: use_cartemu/cfg_write_enable 7: d<1>.PIN 24: use_cartemu/N4/use_cartemu/N4_D2 41: use_cartemu/usdx_bank<0> 8: d<0>.PIN 25: use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 42: use_freezer/next_state_FSM_FFd1 9: a<0> 26: use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 43: use_freezer/next_state_FSM_FFd2 10: a<10> 27: use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 44: use_freezer/next_state_FSM_FFd3 11: a<1> 28: use_cartemu/cfg_bank<0> 45: use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2 12: a<2> 29: use_cartemu/cfg_enable 46: use_freezer/rom_bank_0 13: a<3> 30: use_cartemu/cfg_menu 47: use_freezer/rom_bank_1 14: a<4> 31: use_cartemu/cfg_mode<0> 48: use_freezer/rom_bank_2 15: a<5> 32: use_cartemu/cfg_mode<1> 49: use_freezer/use_status_as_ram_address<0> 16: a<6> 33: use_cartemu/cfg_mode<2> 50: use_pia/pia_crb2 17: a<7> 34: use_cartemu/cfg_source_ram Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2 .XX.....X.XXX....XX..XX.....................X....X.......... 12 use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2 .XX.....X.XXX....XX..XX.....................X....X.......... 12 use_pia/pia_crb2 .XX..X..X.XXX....XX..XX.....................X....X.......... 13 use_cartemu/cfg_usdx<1> X.....X.X.X.X...X...XXX...X........X..X..................... 12 use_cartemu/cfg_usdx<0> X......XX.X.X...X...XXX...X........X.X...................... 12 use_cartemu/cfg_source_ram X.....X.X.XXX...X...XXX...X......X.......................... 12 use_cartemu/cfg_mode<2> X....X..X.XXX...X...XXX...X.....X........................... 12 use_cartemu/cfg_mode<1> X.....X.X.XXX...X...XXX...X....X............................ 12 use_cartemu/cfg_sram_enable X......XX.XXX...X....XX...X.........X....................... 11 use_cartemu/cfg_menu X....X..X.XXX...X..XXXX...X..X.............................. 13 use_freezer/use_status_as_ram_address<0> ..X......X....XX.XX...X..................XXXX...X........... 12 use_freezer/rom_bank_2 ..X......X.X...X.XX......................XXX...X............ 10 use_freezer/rom_bank_1 ..X......XX....X.XX......................XXX..X............. 10 use_freezer/rom_bank_0 ..X.....XX.....X.XX......................XXX.X.............. 10 use_cartemu/trig3_disable_atari X.XX....XXXXX....XX...X.XX..XXXXX........................... 18 $OpTx$INV$490 .......................XXX...XXXXX...XX..................... 10 refresh ....X....................................................... 1 use_cartemu/N50/use_cartemu/N50_D2 ........X.XX.XXX...........XX.X...X.XXXXX................... 15 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$BIN_STEP$760 <= ((NOT a(1) AND a(7) AND NOT a(3) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT a(2) AND a(7) AND NOT a(3) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (a(6) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND NOT use_cartemu/cfg_mode(1) AND NOT a(7) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508) OR (NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(7) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508) OR ( use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (a(14) AND a(15) AND NOT a(12) AND NOT oldos_n) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508) OR (a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499)); $OpTx$FX_DC$499 <= (NOT a(6) AND NOT a(5) AND a(4)); $OpTx$FX_DC$508 <= (NOT a(6) AND NOT a(5) AND NOT a(4)); $OpTx$FX_DC$510 <= ((use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (a(6) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499)); $OpTx$FX_DC$521 <= (a(14) AND a(15) AND NOT a(11) AND NOT a(13) AND NOT a(7) AND a(12)); $OpTx$FX_DC$522 <= (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(1)); $OpTx$FX_DC$538 <= ((merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_SC$591) OR (NOT a(13) AND NOT a(12) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(14) AND a(15) AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2)); $OpTx$FX_DC$540 <= ((use_cartemu/cfg_sram_bank(5) AND use_cartemu/N4/use_cartemu/N4_D2) OR (use_cartemu/cfg_bank(5) AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (use_cartemu/usdx_bank(5) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2)); $OpTx$FX_DC$571 <= ((NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_sram_bank(1) AND use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_bank(1) AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/usdx_bank(1) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2)); $OpTx$FX_DC$577 <= ((use_cartemu/cfg_menu) OR (use_cartemu/cfg_bank(6) AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (use_cartemu/cfg_usdx(0) AND use_cartemu/cfg_usdx(1) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2)); $OpTx$FX_DC$580 <= (a(9) AND a(8) AND a(10) AND NOT a(6) AND NOT a(4) AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2); $OpTx$FX_DC$601 <= ((use_cartemu/cfg_mode(1)) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/oss_bank(0) AND NOT use_cartemu/oss_bank(1))); $OpTx$FX_DC$608 <= ((use_cartemu/cfg_sram_bank(0) AND use_cartemu/N4/use_cartemu/N4_D2) OR (use_cartemu/usdx_bank(0) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND use_cartemu/N29/use_cartemu/N29_D2)); $OpTx$FX_SC$586 <= (a(9) AND a(8) AND a(10) AND a(7)); $OpTx$FX_SC$591 <= (a(14) AND a(15) AND NOT rw AND NOT a(11) AND NOT a(13) AND a(12) AND NOT use_freezer/state(1) AND NOT use_freezer/state(2)); $OpTx$INV$490 <= ((use_cartemu/cfg_menu) OR (NOT use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND NOT use_cartemu/cfg_mode(1) AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_usdx(0) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (use_cartemu/cfg_usdx(1) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_source_ram AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2)); N0/N0_TRST <= ((freezer_mem_dout(5)/freezer_mem_dout(5)_D2) OR (a(14) AND a(15) AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (NOT a(14) AND NOT a(15) AND use_freezer/state(1) AND NOT use_freezer/state(2) AND NOT use_freezer/state(0)) OR (NOT a(14) AND NOT a(15) AND NOT use_freezer/state(1) AND use_freezer/state(2) AND NOT use_freezer/state(0)) OR (a(14) AND a(15) AND NOT a(11) AND a(9) AND a(8) AND a(10) AND NOT a(13) AND a(12) AND NOT use_freezer/state(1) AND use_freezer/state(2)) OR (a(14) AND a(15) AND NOT a(11) AND a(9) AND a(8) AND a(10) AND NOT a(13) AND a(12) AND use_freezer/state(1) AND NOT use_freezer/state(2) AND NOT use_freezer/state(0)) OR (use_cartemu/trig3_disable_atari AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$BIN_STEP$760)); FDCPE_activate_n_sync0: FDCPE port map (activate_n_sync(0),activate_n_in,NOT phi2,'0','0'); FDCPE_activate_n_sync1: FDCPE port map (activate_n_sync(1),activate_n_sync(0),NOT phi2,'0','0'); d_I(0) <= ((rw AND a(7) AND NOT a(3) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/N50/use_cartemu/N50_D2) OR (use_cartemu/trig3_disable_atari AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (NOT use_freezer/state(1) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND freezer_mem_dout(5)/freezer_mem_dout(5)_D2)); d(0) <= d_I(0) when d_OE(0) = '1' else 'Z'; d_OE(0) <= dout_enable; d_I(1) <= ((rw AND use_cartemu/cfg_mode(1) AND NOT a(1) AND a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499) OR (rw AND a(1) AND use_cartemu/cfg_usdx(1) AND a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499) OR (rw AND NOT a(1) AND a(2) AND a(7) AND use_cartemu/cfg_source_ram AND NOT a(3) AND a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499) OR (rw AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (rw AND a(1) AND NOT a(2) AND a(7) AND use_cartemu/cfg_sram_bank(1) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499) OR (rw AND NOT a(1) AND NOT a(2) AND use_cartemu/cfg_bank(1) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499)); d(1) <= d_I(1) when d_OE(1) = '1' else 'Z'; d_OE(1) <= dout_enable; d_I(2) <= ((rw AND use_cartemu/cfg_mode(2) AND NOT a(1) AND a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499) OR (rw AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(2) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (rw AND use_cartemu/cfg_menu AND NOT a(1) AND a(2) AND a(7) AND NOT a(3) AND a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499) OR (rw AND a(1) AND NOT a(2) AND a(7) AND use_cartemu/cfg_sram_bank(2) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499) OR (rw AND NOT a(1) AND NOT a(2) AND use_cartemu/cfg_bank(2) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_DC$499)); d(2) <= d_I(2) when d_OE(2) = '1' else 'Z'; d_OE(2) <= dout_enable; d_I(3) <= ((rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(0) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(3) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(1) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(3) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND NOT a(6) AND NOT a(5) AND a(1) AND NOT a(2) AND a(4) AND a(7) AND use_cartemu/cfg_sram_bank(3) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND NOT a(6) AND NOT a(5) AND NOT a(1) AND NOT a(2) AND use_cartemu/cfg_bank(3) AND a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2)); d(3) <= d_I(3) when d_OE(3) = '1' else 'Z'; d_OE(3) <= dout_enable; d_I(4) <= ((rw AND NOT a(6) AND NOT a(5) AND a(1) AND NOT a(2) AND a(4) AND a(7) AND use_cartemu/cfg_sram_bank(4) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND NOT a(6) AND NOT a(5) AND NOT a(1) AND NOT a(2) AND use_cartemu/cfg_bank(4) AND a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(0) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(4) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(1) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(4) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2)); d(4) <= d_I(4) when d_OE(4) = '1' else 'Z'; d_OE(4) <= dout_enable; d_I(5) <= ((rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(0) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(5) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (merged_out_dout_or0000/merged_out_dout_or0000_D2 AND freezer_mem_dout(5)/freezer_mem_dout(5)_D2) OR (rw AND NOT a(6) AND NOT a(5) AND a(1) AND NOT a(2) AND a(4) AND a(7) AND use_cartemu/cfg_sram_bank(5) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND NOT a(6) AND NOT a(5) AND NOT a(1) AND NOT a(2) AND use_cartemu/cfg_bank(5) AND a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(1) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_bank(5) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2)); d(5) <= d_I(5) when d_OE(5) = '1' else 'Z'; d_OE(5) <= dout_enable; d_I(6) <= ((rw AND NOT a(6) AND NOT a(5) AND NOT a(1) AND NOT a(2) AND a(4) AND a(7) AND use_cartemu/cfg_bank(6) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(0) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_ctl(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(1) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/usdx_ctl(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2)); d(6) <= d_I(6) when d_OE(6) = '1' else 'Z'; d_OE(6) <= dout_enable; d_I(7) <= (rw AND use_cartemu/usdx_ctl(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2); d(7) <= d_I(7) when d_OE(7) = '1' else 'Z'; d_OE(7) <= dout_enable; dout_enable <= ((rw AND a(6) AND a(5) AND phi2 AND NOT a(1) AND use_cartemu/cfg_usdx(0) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND a(6) AND a(5) AND phi2 AND NOT a(1) AND use_cartemu/cfg_usdx(1) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND phi2 AND use_cartemu/trig3_disable_atari AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND phi2 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND freezer_mem_dout(5)/freezer_mem_dout(5)_D2) OR (rw AND NOT a(6) AND NOT a(5) AND phi2 AND NOT a(1) AND a(4) AND a(7) AND NOT a(3) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND NOT a(6) AND NOT a(5) AND phi2 AND NOT a(2) AND a(4) AND a(7) AND NOT a(3) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (rw AND NOT a(6) AND NOT a(5) AND phi2 AND a(4) AND a(7) AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2)); freezer_mem_dout(5)/freezer_mem_dout(5)_D2 <= ((a(14) AND a(15) AND rw AND a(11) AND a(9) AND a(8) AND a(10) AND a(6) AND a(5) AND a(13) AND a(4) AND a(7) AND a(3) AND a(0) AND a(12) AND use_freezer/state(1) AND NOT use_freezer/state(2) AND NOT use_freezer/state(0)) OR (a(14) AND a(15) AND rw AND a(11) AND a(9) AND a(8) AND a(10) AND a(6) AND a(5) AND a(13) AND a(4) AND a(7) AND a(3) AND a(0) AND a(12) AND NOT use_freezer/state(1) AND NOT use_freezer/state(2) AND use_freezer/state(0))); merged_out_dout_or0000/merged_out_dout_or0000_D2 <= ((freezer_mem_dout(5)/freezer_mem_dout(5)_D2) OR (a(14) AND a(15) AND NOT a(11) AND a(9) AND a(8) AND a(10) AND NOT a(13) AND a(12) AND use_freezer/state(1) AND NOT use_freezer/state(2) AND NOT use_freezer/state(0)) OR (NOT a(14) AND NOT a(15) AND use_freezer/state(1) AND NOT use_freezer/state(2) AND NOT use_freezer/state(0)) OR (NOT a(14) AND NOT a(15) AND NOT use_freezer/state(1) AND use_freezer/state(2) AND NOT use_freezer/state(0)) OR (a(14) AND a(15) AND NOT rw AND NOT a(11) AND NOT a(13) AND a(12) AND NOT use_freezer/state(1) AND NOT use_freezer/state(2)) OR (a(14) AND a(15) AND NOT a(11) AND a(9) AND a(8) AND a(10) AND NOT a(13) AND a(12) AND NOT use_freezer/state(1) AND use_freezer/state(2))); FTCPE_powerup_n: FTCPE port map (powerup_n,'1',NOT phi2,'0','0',powerup_n_CE); powerup_n_CE <= (NOT powerup_n AND reset_n_sync(2) AND NOT reset_n_sync(3)); ram0_ce <= NOT (((phi2 AND oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT a(14) AND NOT a(15) AND phi2 AND NOT a(13) AND use_freezer/state(1) AND NOT use_freezer/state(2) AND NOT use_freezer/state(0) AND merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (NOT a(14) AND NOT a(15) AND phi2 AND NOT a(13) AND NOT use_freezer/state(1) AND use_freezer/state(2) AND NOT use_freezer/state(0) AND merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (a(14) AND a(15) AND NOT rw AND NOT a(11) AND phi2 AND NOT a(13) AND a(12) AND NOT use_freezer/state(1) AND NOT use_freezer/state(2) AND merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (NOT a(14) AND phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT a(15) AND phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (phi2 AND NOT a(13) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2))); ram1_ce <= NOT (((phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND $OpTx$FX_DC$577) OR (a(14) AND a(15) AND phi2 AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2))); ram_a(4) <= ((a(14) AND a(15) AND a(13) AND a(4) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (NOT a(9) AND NOT a(8) AND NOT a(10) AND a(4) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_SC$591) OR (NOT a(8) AND NOT a(10) AND a(4) AND NOT dualpokey_n AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_SC$591) OR (a(4) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (a(4) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (a(13) AND a(4) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(4) AND NOT use_freezer/use_status_as_ram_address(0) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT a(13) AND use_freezer/use_status_as_ram_address(0) AND use_freezer/vector_a2 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2)); ram_a(5) <= ((a(14) AND a(15) AND a(5) AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (a(5) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (a(5) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (a(5) AND a(13) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(5) AND NOT use_freezer/use_status_as_ram_address(0) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT a(13) AND use_freezer/use_status_as_ram_address(0) AND NOT dualpokey_n AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2)); ram_a(6) <= ((a(6) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(6) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (a(6) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (a(14) AND a(15) AND a(6) AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2)); ram_a(7) <= ((a(7) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(7) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (a(7) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (a(14) AND a(15) AND a(13) AND a(7) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2)); ram_rom_a(12) <= ((a(13) AND a(12) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT a(13) AND NOT a(12) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT a(13) AND use_freezer/ram_bank_0 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (NOT use_cartemu/oss_bank(0) AND NOT use_cartemu/oss_bank(1) AND a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (a(14) AND a(15) AND a(13) AND a(12) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (use_cartemu/cfg_mode(0) AND NOT use_cartemu/cfg_menu AND use_cartemu/oss_bank(0) AND NOT a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND $OpTx$FX_DC$522 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_SC$591) OR (a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT use_cartemu/cfg_mode(0) AND a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (use_cartemu/cfg_menu AND a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT $OpTx$FX_DC$522 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2)); ram_rom_a(13) <= (($OpTx$FX_DC$538) OR (a(13) AND use_freezer/rom_bank_0 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT a(13) AND use_freezer/ram_bank_1 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT use_cartemu/cfg_menu AND use_cartemu/cfg_bank(0) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND use_cartemu/N29/use_cartemu/N29_D2) OR (NOT use_cartemu/cfg_mode(0) AND NOT use_cartemu/cfg_menu AND a(13) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND $OpTx$FX_DC$522 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (use_cartemu/cfg_mode(0) AND NOT use_cartemu/cfg_menu AND use_cartemu/oss_bank(1) AND NOT a(12) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND $OpTx$FX_DC$522 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (a(13) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT use_cartemu/cfg_menu AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND $OpTx$FX_DC$608)); ram_rom_a(14) <= (($OpTx$FX_DC$538) OR (use_pia/pia_portb(2) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (a(13) AND use_freezer/rom_bank_1 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT a(13) AND use_freezer/ram_bank_2 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT use_pia/pia_ddrb(2) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$571)); ram_rom_a(15) <= (($OpTx$FX_DC$538) OR (a(13) AND use_freezer/rom_bank_2 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT use_pia/pia_ddrb(3) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (use_pia/pia_portb(3) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2) OR (NOT a(13) AND use_freezer/ram_bank_3 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2)); ram_rom_a(16) <= (($OpTx$FX_DC$538) OR (use_pia/pia_portb(5) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (a(13) AND use_freezer/rom_bank_3 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT a(13) AND use_freezer/ram_bank_4 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT use_pia/pia_ddrb(5) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2)); ram_rom_a(17) <= ((use_freezer/rom_bank_4 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(14) AND a(15) AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_SC$591) OR (NOT a(13) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (NOT use_pia/pia_ddrb(6) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (use_pia/pia_portb(6) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2)); ram_rom_a(18) <= ((NOT a(13) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (use_freezer/rom_bank_5 AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (a(14) AND a(15) AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2) OR (merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$FX_SC$591) OR (use_cartemu/cfg_menu AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (NOT use_pia/pia_ddrb(7) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (use_pia/pia_portb(7) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND $OpTx$FX_DC$540)); ram_rom_oe <= NOT ((rw AND phi2)); ram_rom_we <= NOT ((NOT rw AND phi2short)); ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2 <= (a(14) AND NOT ramdisk_enable_n AND NOT a(15) AND use_pia/pia_ddrb(4) AND NOT use_pia/pia_portb(4)); refresh_I <= '0'; refresh <= refresh_I when refresh_OE = '1' else 'Z'; refresh_OE <= N0/N0_TRST; FDCPE_reset_n_sync0: FDCPE port map (reset_n_sync(0),reset_n_in,NOT phi2,'0','0'); FDCPE_reset_n_sync1: FDCPE port map (reset_n_sync(1),reset_n_sync(0),NOT phi2,'0','0'); FDCPE_reset_n_sync2: FDCPE port map (reset_n_sync(2),reset_n_sync(1),NOT phi2,'0','0'); FDCPE_reset_n_sync3: FDCPE port map (reset_n_sync(3),reset_n_sync(2),NOT phi2,'0','0'); rom0_ce <= NOT (((NOT a(15) AND phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (phi2 AND NOT a(13) AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (phi2 AND oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (NOT a(14) AND phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND NOT $OpTx$FX_DC$577 AND NOT ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2))); rom1_ce <= NOT (((a(14) AND a(15) AND phi2 AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2) OR (phi2 AND a(13) AND merged_out_dout_or0000/merged_out_dout_or0000_D2 AND use_freezer/N24/use_freezer/N24_D2) OR (phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND $OpTx$FX_DC$577) OR (phi2 AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2 AND $OpTx$INV$490 AND NOT use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 AND ramdisk_mem_adr(19)/ramdisk_mem_adr(19)_D2) OR (a(14) AND a(15) AND rw AND phi2 AND a(13) AND NOT oldos_n AND NOT merged_out_dout_or0000/merged_out_dout_or0000_D2))); use_cartemu/N29/use_cartemu/N29_D2 <= (( NOT use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2) OR (use_cartemu/cfg_mode(0) AND NOT use_cartemu/oss_bank(0) AND NOT use_cartemu/oss_bank(1)) OR (NOT $OpTx$FX_DC$522 AND NOT use_cartemu/N4/use_cartemu/N4_D2)); use_cartemu/N4/use_cartemu/N4_D2 <= (NOT a(14) AND a(15) AND NOT use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(13) AND use_cartemu/cfg_sram_enable AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2); use_cartemu/N50/use_cartemu/N50_D2 <= ((NOT a(6) AND NOT a(5) AND a(1) AND use_cartemu/cfg_usdx(0) AND a(2) AND a(4) AND NOT a(0)) OR (NOT a(6) AND NOT a(5) AND a(1) AND NOT a(2) AND a(4) AND use_cartemu/cfg_sram_bank(0) AND NOT a(0)) OR (a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(0) AND NOT a(2) AND NOT a(4) AND NOT a(0) AND use_cartemu/usdx_bank(0)) OR (a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(1) AND NOT a(2) AND NOT a(4) AND NOT a(0) AND use_cartemu/usdx_bank(0)) OR (NOT a(6) AND NOT a(5) AND use_cartemu/cfg_mode(0) AND NOT a(1) AND a(2) AND a(4) AND NOT a(0)) OR (NOT a(6) AND NOT a(5) AND a(1) AND use_cartemu/cfg_sram_enable AND NOT a(2) AND a(4) AND a(0)) OR (NOT a(6) AND NOT a(5) AND NOT a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND a(4) AND a(0)) OR (NOT a(6) AND NOT a(5) AND NOT a(1) AND a(2) AND a(4) AND use_cartemu/cfg_write_enable AND a(0)) OR (NOT a(6) AND NOT a(5) AND NOT a(1) AND NOT a(2) AND use_cartemu/cfg_bank(0) AND a(4) AND NOT a(0))); use_cartemu/N97/use_cartemu/N97_D2 <= ((a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(0) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0)) OR (a(6) AND a(5) AND NOT a(1) AND use_cartemu/cfg_usdx(1) AND NOT a(2) AND NOT a(4) AND a(7) AND NOT a(3) AND NOT a(0))); use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 <= ((NOT use_cartemu/cfg_usdx(0) AND NOT use_cartemu/cfg_usdx(1)) OR (NOT use_cartemu/usdx_ctl(0) AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2)); use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2 <= ((NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_sram_bank(2) AND use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_bank(2) AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/usdx_bank(2) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2)); use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2 <= ((NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_sram_bank(3) AND use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_bank(3) AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/usdx_bank(3) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2)); use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2 <= ((NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_sram_bank(4) AND use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/cfg_bank(4) AND NOT use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT use_cartemu/cfg_menu AND NOT use_cartemu/usdx_bank(4) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2)); use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 <= ((use_cartemu/cfg_usdx(0) AND NOT use_cartemu/usdx_ctl(1)) OR (use_cartemu/cfg_usdx(1) AND NOT use_cartemu/usdx_ctl(1))); use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2 <= ((NOT a(14) AND a(15) AND use_cartemu/cfg_enable AND a(13) AND NOT use_cartemu/N29/use_cartemu/N29_D2) OR (NOT a(14) AND a(15) AND NOT use_cartemu/cfg_mode(0) AND NOT use_cartemu/cfg_menu AND use_cartemu/cfg_enable AND NOT use_cartemu/N29/use_cartemu/N29_D2) OR (NOT a(14) AND a(15) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_enable AND a(13) AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2) OR (NOT a(14) AND a(15) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND use_cartemu/cfg_enable AND a(13) AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2) OR (NOT use_cartemu/cfg_menu AND use_cartemu/N4/use_cartemu/N4_D2) OR (NOT a(14) AND a(15) AND use_cartemu/cfg_menu AND a(13)) OR (NOT a(14) AND a(15) AND a(13) AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2)); use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 <= ((a(14) AND a(15) AND NOT a(11) AND NOT a(9) AND a(8) AND a(10) AND NOT a(13) AND a(12) AND NOT flash_we_n) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(9) AND a(8) AND a(10) AND NOT a(13) AND a(12) AND NOT cartemu_enable_n)); FDCPE_use_cartemu/cfg_bank0: FDCPE port map (use_cartemu/cfg_bank(0),use_cartemu/cfg_bank_D(0),NOT phi2short,'0','0'); use_cartemu/cfg_bank_D(0) <= ((NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND d(0).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (use_cartemu/cfg_bank(0) AND NOT $OpTx$FX_DC$510) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (a(6) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2)); FDCPE_use_cartemu/cfg_bank1: FDCPE port map (use_cartemu/cfg_bank(1),use_cartemu/cfg_bank_D(1),NOT phi2short,'0','0'); use_cartemu/cfg_bank_D(1) <= ((use_cartemu/cfg_bank(1) AND NOT $OpTx$FX_DC$510) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(1) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (a(6) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(1) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND d(1).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499)); FDCPE_use_cartemu/cfg_bank2: FDCPE port map (use_cartemu/cfg_bank(2),use_cartemu/cfg_bank_D(2),NOT phi2short,'0','0'); use_cartemu/cfg_bank_D(2) <= ((a(6) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(2) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND d(2).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (use_cartemu/cfg_bank(2) AND NOT $OpTx$FX_DC$510) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(2) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2)); FDCPE_use_cartemu/cfg_bank3: FDCPE port map (use_cartemu/cfg_bank(3),use_cartemu/cfg_bank_D(3),NOT phi2short,'0','0'); use_cartemu/cfg_bank_D(3) <= ((use_cartemu/cfg_bank(3) AND NOT $OpTx$FX_DC$510) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND a(3) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (a(6) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND a(3) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND d(3).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499)); FDCPE_use_cartemu/cfg_bank4: FDCPE port map (use_cartemu/cfg_bank(4),use_cartemu/cfg_bank_D(4),NOT phi2short,'0','0'); use_cartemu/cfg_bank_D(4) <= ((use_cartemu/cfg_bank(4) AND NOT $OpTx$FX_DC$510) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(4) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (a(6) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(4) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND d(4).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499)); FDCPE_use_cartemu/cfg_bank5: FDCPE port map (use_cartemu/cfg_bank(5),use_cartemu/cfg_bank_D(5),NOT phi2short,'0','0'); use_cartemu/cfg_bank_D(5) <= ((use_cartemu/cfg_bank(5) AND NOT $OpTx$FX_DC$510) OR (a(5) AND use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (a(6) AND a(5) AND NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND d(5).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499)); FTCPE_use_cartemu/cfg_bank6: FTCPE port map (use_cartemu/cfg_bank(6),use_cartemu/cfg_bank_T(6),NOT phi2short,'0','0'); use_cartemu/cfg_bank_T(6) <= ((a(6) AND use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND NOT use_cartemu/cfg_bank(6) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT a(6) AND use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(7) AND use_cartemu/cfg_bank(6) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND use_cartemu/cfg_bank(6) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND NOT d(6).PIN AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT a(1) AND NOT a(2) AND a(7) AND NOT use_cartemu/cfg_bank(6) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND d(6).PIN AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499)); FTCPE_use_cartemu/cfg_enable: FTCPE port map (use_cartemu/cfg_enable,use_cartemu/cfg_enable_T,NOT phi2short,'0','0'); use_cartemu/cfg_enable_T <= ((use_cartemu/cfg_write_enable.EXP) OR (NOT rw AND NOT use_cartemu/cfg_mode(1) AND NOT a(1) AND NOT use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND d(0).PIN AND NOT a(3) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT a(1) AND NOT use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND d(0).PIN AND NOT a(3) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT $OpTx$FX_DC$508) OR (NOT rw AND NOT use_cartemu/cfg_mode(0) AND NOT a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT d(0).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT use_cartemu/cfg_mode(1) AND NOT a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT d(0).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508) OR (NOT rw AND use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND NOT a(1) AND NOT use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND use_cartemu/cfg_mode(2) AND NOT a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT d(0).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND NOT a(1) AND NOT use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT d(0).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT $OpTx$FX_DC$508) OR (NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(1) AND NOT use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508) OR (use_cartemu/cfg_enable AND NOT powerup_n AND NOT reset_n_sync(1)) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT use_cartemu/cfg_enable AND NOT a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2) OR (use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND use_cartemu/cfg_enable AND a(7) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508) OR (NOT rw AND NOT use_cartemu/cfg_mode(1) AND NOT a(1) AND NOT use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT a(1) AND NOT use_cartemu/cfg_enable AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT $OpTx$FX_DC$508)); FTCPE_use_cartemu/cfg_menu: FTCPE port map (use_cartemu/cfg_menu,use_cartemu/cfg_menu_T,NOT phi2short,'0','0'); use_cartemu/cfg_menu_T <= ((use_cartemu/cfg_menu AND NOT powerup_n AND NOT reset_n_sync(1) AND cartemu_enable_n) OR (NOT use_cartemu/cfg_menu AND NOT powerup_n AND NOT reset_n_sync(1) AND NOT cartemu_enable_n) OR (NOT rw AND use_cartemu/cfg_menu AND NOT a(1) AND a(2) AND a(7) AND NOT d(2).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT use_cartemu/cfg_menu AND NOT a(1) AND a(2) AND a(7) AND d(2).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499)); FTCPE_use_cartemu/cfg_mode0: FTCPE port map (use_cartemu/cfg_mode(0),use_cartemu/cfg_mode_T(0),NOT phi2short,'0','0'); use_cartemu/cfg_mode_T(0) <= ((use_cartemu/cfg_mode(0) AND NOT powerup_n AND NOT reset_n_sync(1)) OR (NOT rw AND use_cartemu/cfg_mode(0) AND NOT a(1) AND a(2) AND a(7) AND NOT d(0).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT use_cartemu/cfg_mode(0) AND NOT a(1) AND a(2) AND a(7) AND d(0).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499)); FTCPE_use_cartemu/cfg_mode1: FTCPE port map (use_cartemu/cfg_mode(1),use_cartemu/cfg_mode_T(1),NOT phi2short,'0','0'); use_cartemu/cfg_mode_T(1) <= ((use_cartemu/cfg_mode(1) AND NOT powerup_n AND NOT reset_n_sync(1)) OR (NOT rw AND use_cartemu/cfg_mode(1) AND NOT a(1) AND a(2) AND a(7) AND NOT d(1).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT use_cartemu/cfg_mode(1) AND NOT a(1) AND a(2) AND a(7) AND d(1).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499)); FTCPE_use_cartemu/cfg_mode2: FTCPE port map (use_cartemu/cfg_mode(2),use_cartemu/cfg_mode_T(2),NOT phi2short,'0','0'); use_cartemu/cfg_mode_T(2) <= ((use_cartemu/cfg_mode(2) AND NOT powerup_n AND NOT reset_n_sync(1)) OR (NOT rw AND use_cartemu/cfg_mode(2) AND NOT a(1) AND a(2) AND a(7) AND NOT d(2).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT use_cartemu/cfg_mode(2) AND NOT a(1) AND a(2) AND a(7) AND d(2).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499)); FTCPE_use_cartemu/cfg_source_ram: FTCPE port map (use_cartemu/cfg_source_ram,use_cartemu/cfg_source_ram_T,NOT phi2short,'0','0'); use_cartemu/cfg_source_ram_T <= ((NOT powerup_n AND use_cartemu/cfg_source_ram AND NOT reset_n_sync(1)) OR (NOT rw AND NOT a(1) AND a(2) AND a(7) AND use_cartemu/cfg_source_ram AND NOT d(1).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT a(1) AND a(2) AND a(7) AND NOT use_cartemu/cfg_source_ram AND d(1).PIN AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499)); FDCPE_use_cartemu/cfg_sram_bank0: FDCPE port map (use_cartemu/cfg_sram_bank(0),use_cartemu/cfg_sram_bank_D(0),NOT phi2short,'0','0'); use_cartemu/cfg_sram_bank_D(0) <= ((d(0).PIN AND use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (use_cartemu/cfg_sram_bank(0) AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2)); FDCPE_use_cartemu/cfg_sram_bank1: FDCPE port map (use_cartemu/cfg_sram_bank(1),use_cartemu/cfg_sram_bank_D(1),NOT phi2short,'0','0'); use_cartemu/cfg_sram_bank_D(1) <= ((d(1).PIN AND use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (use_cartemu/cfg_sram_bank(1) AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2)); FDCPE_use_cartemu/cfg_sram_bank2: FDCPE port map (use_cartemu/cfg_sram_bank(2),use_cartemu/cfg_sram_bank_D(2),NOT phi2short,'0','0'); use_cartemu/cfg_sram_bank_D(2) <= ((d(2).PIN AND use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (use_cartemu/cfg_sram_bank(2) AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2)); FDCPE_use_cartemu/cfg_sram_bank3: FDCPE port map (use_cartemu/cfg_sram_bank(3),use_cartemu/cfg_sram_bank_D(3),NOT phi2short,'0','0'); use_cartemu/cfg_sram_bank_D(3) <= ((d(3).PIN AND use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (use_cartemu/cfg_sram_bank(3) AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2)); FDCPE_use_cartemu/cfg_sram_bank4: FDCPE port map (use_cartemu/cfg_sram_bank(4),use_cartemu/cfg_sram_bank_D(4),NOT phi2short,'0','0'); use_cartemu/cfg_sram_bank_D(4) <= ((d(4).PIN AND use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (use_cartemu/cfg_sram_bank(4) AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2)); FDCPE_use_cartemu/cfg_sram_bank5: FDCPE port map (use_cartemu/cfg_sram_bank(5),use_cartemu/cfg_sram_bank_D(5),NOT phi2short,'0','0'); use_cartemu/cfg_sram_bank_D(5) <= ((d(5).PIN AND use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (use_cartemu/cfg_sram_bank(5) AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2)); use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2 <= (NOT rw AND a(1) AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499); FTCPE_use_cartemu/cfg_sram_enable: FTCPE port map (use_cartemu/cfg_sram_enable,use_cartemu/cfg_sram_enable_T,NOT phi2short,'0','0'); use_cartemu/cfg_sram_enable_T <= ((use_cartemu/cfg_sram_enable AND NOT reset_n_sync(1)) OR (NOT rw AND a(1) AND use_cartemu/cfg_sram_enable AND NOT a(2) AND a(7) AND NOT d(0).PIN AND NOT a(3) AND a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND a(1) AND NOT use_cartemu/cfg_sram_enable AND NOT a(2) AND a(7) AND d(0).PIN AND NOT a(3) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND a(1) AND NOT use_cartemu/cfg_sram_enable AND NOT a(2) AND a(7) AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499)); FTCPE_use_cartemu/cfg_usdx0: FTCPE port map (use_cartemu/cfg_usdx(0),use_cartemu/cfg_usdx_T(0),NOT phi2short,'0','0'); use_cartemu/cfg_usdx_T(0) <= ((use_cartemu/cfg_usdx(0) AND NOT powerup_n AND NOT reset_n_sync(1)) OR (NOT rw AND a(1) AND use_cartemu/cfg_usdx(0) AND a(7) AND NOT d(0).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (NOT rw AND a(1) AND NOT use_cartemu/cfg_usdx(0) AND a(7) AND d(0).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2)); FTCPE_use_cartemu/cfg_usdx1: FTCPE port map (use_cartemu/cfg_usdx(1),use_cartemu/cfg_usdx_T(1),NOT phi2short,'0','0'); use_cartemu/cfg_usdx_T(1) <= ((use_cartemu/cfg_usdx(1) AND NOT powerup_n AND NOT reset_n_sync(1)) OR (NOT rw AND a(1) AND use_cartemu/cfg_usdx(1) AND a(7) AND NOT d(1).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2) OR (NOT rw AND a(1) AND NOT use_cartemu/cfg_usdx(1) AND a(7) AND d(1).PIN AND NOT a(3) AND NOT a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2)); FTCPE_use_cartemu/cfg_write_enable: FTCPE port map (use_cartemu/cfg_write_enable,use_cartemu/cfg_write_enable_T,NOT phi2short,'0','0'); use_cartemu/cfg_write_enable_T <= ((NOT rw AND use_cartemu/cfg_mode(2) AND NOT a(1) AND a(2) AND a(7) AND NOT d(0).PIN AND use_cartemu/cfg_write_enable AND NOT a(3) AND a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT use_cartemu/cfg_mode(0) AND NOT a(1) AND a(2) AND a(7) AND NOT d(0).PIN AND use_cartemu/cfg_write_enable AND NOT a(3) AND a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT a(1) AND a(2) AND a(7) AND d(0).PIN AND NOT use_cartemu/cfg_write_enable AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT rw AND NOT a(1) AND a(2) AND a(7) AND NOT d(0).PIN AND use_cartemu/cfg_write_enable AND NOT a(3) AND a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499 AND NOT $OpTx$FX_DC$508) OR (NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(1) AND a(2) AND a(7) AND NOT use_cartemu/cfg_write_enable AND NOT a(3) AND a(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508) OR (use_cartemu/cfg_write_enable AND NOT reset_n_sync(1)) OR (NOT rw AND NOT use_cartemu/cfg_mode(1) AND NOT a(1) AND a(2) AND a(7) AND NOT d(0).PIN AND use_cartemu/cfg_write_enable AND NOT a(3) AND a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$499) OR (NOT use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND NOT a(1) AND a(2) AND a(7) AND use_cartemu/cfg_write_enable AND NOT a(3) AND NOT a(0) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508)); use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 <= (( NOT use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2) OR (NOT rw AND use_cartemu/cfg_mode(2) AND use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT rw AND NOT use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND NOT use_cartemu/cfg_mode(1) AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT $OpTx$INV$490 AND NOT use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2 AND NOT use_cartemu/address_16_mux0003/use_cartemu/address_16_mux0003_D2 AND NOT $OpTx$FX_DC$571 AND NOT use_cartemu/address_17_mux0003/use_cartemu/address_17_mux0003_D2 AND $OpTx$FX_DC$540) OR (NOT rw AND use_cartemu/cfg_menu) OR (NOT $OpTx$INV$490 AND $OpTx$FX_DC$577) OR (NOT rw AND NOT use_cartemu/cfg_write_enable AND NOT use_cartemu/N4/use_cartemu/N4_D2) OR (NOT rw AND flash_we_n AND NOT use_cartemu/N4/use_cartemu/N4_D2)); FTCPE_use_cartemu/oss_bank0: FTCPE port map (use_cartemu/oss_bank(0),use_cartemu/oss_bank_T(0),NOT phi2short,'0','0'); use_cartemu/oss_bank_T(0) <= ((use_cartemu/cfg_mode(0) AND NOT a(7) AND a(3) AND use_cartemu/oss_bank(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$522) OR (use_cartemu/cfg_mode(0) AND NOT a(7) AND NOT a(3) AND NOT use_cartemu/oss_bank(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$522)); FTCPE_use_cartemu/oss_bank1: FTCPE port map (use_cartemu/oss_bank(1),use_cartemu/oss_bank_T(1),NOT phi2short,'0','0'); use_cartemu/oss_bank_T(1) <= ((use_cartemu/cfg_mode(0) AND NOT a(7) AND a(0) AND NOT use_cartemu/oss_bank(1) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$522) OR (use_cartemu/cfg_mode(0) AND NOT a(7) AND NOT a(0) AND use_cartemu/oss_bank(1) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$522)); use_cartemu/trig3_disable_atari <= ((rw AND NOT a(9) AND NOT a(8) AND NOT a(10) AND use_cartemu/cfg_menu AND a(1) AND NOT a(2) AND NOT a(3) AND a(0) AND $OpTx$FX_DC$499 AND $OpTx$FX_DC$521) OR (rw AND NOT a(9) AND NOT a(8) AND NOT a(10) AND a(1) AND NOT a(2) AND NOT a(3) AND a(0) AND $OpTx$FX_DC$499 AND NOT use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 AND $OpTx$FX_DC$521) OR (rw AND NOT a(9) AND NOT a(8) AND NOT a(10) AND use_cartemu/cfg_mode(2) AND NOT use_cartemu/cfg_mode(0) AND a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND NOT a(3) AND a(0) AND $OpTx$FX_DC$499 AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND $OpTx$FX_DC$521) OR (rw AND NOT a(9) AND NOT a(8) AND NOT a(10) AND use_cartemu/cfg_mode(0) AND a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND NOT a(3) AND a(0) AND $OpTx$FX_DC$499 AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND $OpTx$FX_DC$521 AND NOT $OpTx$FX_DC$601) OR (rw AND NOT a(9) AND NOT a(8) AND NOT a(10) AND NOT use_cartemu/cfg_mode(0) AND use_cartemu/cfg_mode(1) AND a(1) AND use_cartemu/cfg_enable AND NOT a(2) AND NOT a(3) AND a(0) AND $OpTx$FX_DC$499 AND use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 AND $OpTx$FX_DC$521)); FTCPE_use_cartemu/usdx_bank0: FTCPE port map (use_cartemu/usdx_bank(0),use_cartemu/usdx_bank_T(0),NOT phi2short,'0','0'); use_cartemu/usdx_bank_T(0) <= ((NOT rw AND d(0).PIN AND NOT use_cartemu/usdx_bank(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT d(0).PIN AND use_cartemu/usdx_bank(0) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2)); FTCPE_use_cartemu/usdx_bank1: FTCPE port map (use_cartemu/usdx_bank(1),use_cartemu/usdx_bank_T(1),NOT phi2short,'0','0'); use_cartemu/usdx_bank_T(1) <= ((NOT rw AND d(1).PIN AND NOT use_cartemu/usdx_bank(1) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT d(1).PIN AND use_cartemu/usdx_bank(1) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2)); FTCPE_use_cartemu/usdx_bank2: FTCPE port map (use_cartemu/usdx_bank(2),use_cartemu/usdx_bank_T(2),NOT phi2short,'0','0'); use_cartemu/usdx_bank_T(2) <= ((NOT rw AND d(2).PIN AND NOT use_cartemu/usdx_bank(2) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT d(2).PIN AND use_cartemu/usdx_bank(2) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2)); FTCPE_use_cartemu/usdx_bank3: FTCPE port map (use_cartemu/usdx_bank(3),use_cartemu/usdx_bank_T(3),NOT phi2short,'0','0'); use_cartemu/usdx_bank_T(3) <= ((NOT rw AND d(3).PIN AND NOT use_cartemu/usdx_bank(3) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT d(3).PIN AND use_cartemu/usdx_bank(3) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2)); FTCPE_use_cartemu/usdx_bank4: FTCPE port map (use_cartemu/usdx_bank(4),use_cartemu/usdx_bank_T(4),NOT phi2short,'0','0'); use_cartemu/usdx_bank_T(4) <= ((NOT rw AND d(4).PIN AND NOT use_cartemu/usdx_bank(4) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT d(4).PIN AND use_cartemu/usdx_bank(4) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2)); FTCPE_use_cartemu/usdx_bank5: FTCPE port map (use_cartemu/usdx_bank(5),use_cartemu/usdx_bank_T(5),NOT phi2short,'0','0'); use_cartemu/usdx_bank_T(5) <= ((NOT rw AND d(5).PIN AND NOT use_cartemu/usdx_bank(5) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT d(5).PIN AND use_cartemu/usdx_bank(5) AND reset_n_sync(1) AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2)); FTCPE_use_cartemu/usdx_ctl0: FTCPE port map (use_cartemu/usdx_ctl(0),use_cartemu/usdx_ctl_T(0),NOT phi2short,'0','0'); use_cartemu/usdx_ctl_T(0) <= ((NOT powerup_n AND use_cartemu/usdx_ctl(0) AND NOT reset_n_sync(1)) OR (NOT rw AND use_cartemu/usdx_ctl(0) AND reset_n_sync(1) AND NOT d(6).PIN AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT use_cartemu/usdx_ctl(0) AND reset_n_sync(1) AND d(6).PIN AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2)); FTCPE_use_cartemu/usdx_ctl1: FTCPE port map (use_cartemu/usdx_ctl(1),use_cartemu/usdx_ctl_T(1),NOT phi2short,'0','0'); use_cartemu/usdx_ctl_T(1) <= ((NOT powerup_n AND NOT use_cartemu/usdx_ctl(1) AND NOT reset_n_sync(1)) OR (NOT rw AND use_cartemu/usdx_ctl(1) AND reset_n_sync(1) AND NOT d(7).PIN AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2) OR (NOT rw AND NOT use_cartemu/usdx_ctl(1) AND reset_n_sync(1) AND d(7).PIN AND use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 AND use_cartemu/N97/use_cartemu/N97_D2)); use_freezer/N24/use_freezer/N24_D2 <= ((NOT a(14) AND NOT a(15) AND use_freezer/state(1) AND NOT use_freezer/state(2) AND NOT use_freezer/state(0)) OR (NOT a(14) AND NOT a(15) AND NOT use_freezer/state(1) AND use_freezer/state(2) AND NOT use_freezer/state(0))); FDCPE_use_freezer/next_state_FSM_FFd1: FDCPE port map (use_freezer/next_state_FSM_FFd1,use_freezer/next_state_FSM_FFd1_D,NOT phi2short,'0','0'); use_freezer/next_state_FSM_FFd1_D <= ((NOT rw AND reset_n_sync(1) AND use_freezer/next_state_FSM_FFd1) OR (reset_n_sync(1) AND use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2) OR (reset_n_sync(1) AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$580)); FDCPE_use_freezer/next_state_FSM_FFd2: FDCPE port map (use_freezer/next_state_FSM_FFd2,use_freezer/next_state_FSM_FFd2_D,NOT phi2short,'0','0'); use_freezer/next_state_FSM_FFd2_D <= ((reset_n_sync(1) AND use_freezer/next_state_FSM_FFd2 AND NOT $OpTx$FX_DC$580) OR (a(14) AND a(15) AND rw AND a(11) AND a(6) AND a(5) AND a(13) AND a(4) AND a(3) AND a(0) AND a(12) AND reset_n_sync(1) AND NOT use_freezer/next_state_FSM_FFd1 AND use_freezer/next_state_FSM_FFd3 AND NOT activate_n_sync(1) AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND rw AND a(11) AND a(6) AND a(5) AND a(13) AND a(4) AND a(3) AND a(0) AND a(12) AND reset_n_sync(1) AND NOT use_freezer/next_state_FSM_FFd1 AND use_freezer/next_state_FSM_FFd2 AND NOT activate_n_sync(1) AND $OpTx$FX_SC$586)); FDCPE_use_freezer/next_state_FSM_FFd3: FDCPE port map (use_freezer/next_state_FSM_FFd3,use_freezer/next_state_FSM_FFd3_D,NOT phi2short,'0','0'); use_freezer/next_state_FSM_FFd3_D <= ((reset_n_sync(1) AND use_freezer/next_state_FSM_FFd1 AND use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2) OR (NOT rw AND reset_n_sync(1) AND use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2) OR (a(14) AND a(15) AND rw AND a(11) AND a(6) AND a(5) AND a(13) AND a(4) AND a(3) AND NOT a(0) AND a(12) AND reset_n_sync(1) AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2 AND NOT activate_n_sync(1) AND $OpTx$FX_SC$586)); use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2 <= (a(9) AND a(8) AND a(10) AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$521); FTCPE_use_freezer/ram_bank_0: FTCPE port map (use_freezer/ram_bank_0,use_freezer/ram_bank_0_T,NOT phi2short,'0','0'); use_freezer/ram_bank_0_T <= ((use_freezer/ram_bank_0 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND NOT a(0) AND a(12) AND use_freezer/ram_bank_0 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(0) AND a(12) AND NOT use_freezer/ram_bank_0 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(0) AND a(12) AND NOT use_freezer/ram_bank_0 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(0) AND a(12) AND NOT use_freezer/ram_bank_0 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_SC$586)); FTCPE_use_freezer/ram_bank_1: FTCPE port map (use_freezer/ram_bank_1,use_freezer/ram_bank_1_T,NOT phi2short,'0','0'); use_freezer/ram_bank_1_T <= ((use_freezer/ram_bank_1 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(1) AND NOT a(13) AND a(12) AND use_freezer/ram_bank_1 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND a(1) AND NOT a(13) AND a(12) AND NOT use_freezer/ram_bank_1 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND a(1) AND NOT a(13) AND a(12) AND NOT use_freezer/ram_bank_1 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND a(1) AND NOT a(13) AND a(12) AND NOT use_freezer/ram_bank_1 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_SC$586)); FTCPE_use_freezer/ram_bank_2: FTCPE port map (use_freezer/ram_bank_2,use_freezer/ram_bank_2_T,NOT phi2short,'0','0'); use_freezer/ram_bank_2_T <= ((use_freezer/ram_bank_2 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND NOT a(2) AND a(12) AND use_freezer/ram_bank_2 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(2) AND a(12) AND NOT use_freezer/ram_bank_2 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(2) AND a(12) AND NOT use_freezer/ram_bank_2 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(2) AND a(12) AND NOT use_freezer/ram_bank_2 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_SC$586)); FTCPE_use_freezer/ram_bank_3: FTCPE port map (use_freezer/ram_bank_3,use_freezer/ram_bank_3_T,NOT phi2short,'0','0'); use_freezer/ram_bank_3_T <= ((use_freezer/ram_bank_3 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND NOT a(3) AND a(12) AND use_freezer/ram_bank_3 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(3) AND a(12) AND NOT use_freezer/ram_bank_3 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(3) AND a(12) AND NOT use_freezer/ram_bank_3 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(3) AND a(12) AND NOT use_freezer/ram_bank_3 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_SC$586)); FTCPE_use_freezer/ram_bank_4: FTCPE port map (use_freezer/ram_bank_4,use_freezer/ram_bank_4_T,NOT phi2short,'0','0'); use_freezer/ram_bank_4_T <= ((use_freezer/ram_bank_4 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND NOT a(4) AND a(12) AND use_freezer/ram_bank_4 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(4) AND a(12) AND NOT use_freezer/ram_bank_4 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(4) AND a(12) AND NOT use_freezer/ram_bank_4 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_SC$586) OR (a(14) AND a(15) AND NOT a(11) AND NOT a(6) AND NOT a(5) AND NOT a(13) AND a(4) AND a(12) AND NOT use_freezer/ram_bank_4 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_SC$586)); FTCPE_use_freezer/rom_bank_0: FTCPE port map (use_freezer/rom_bank_0,use_freezer/rom_bank_0_T,NOT phi2short,'0','0'); use_freezer/rom_bank_0_T <= ((use_freezer/rom_bank_0 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(0) AND use_freezer/rom_bank_0 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(0) AND NOT use_freezer/rom_bank_0 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(0) AND NOT use_freezer/rom_bank_0 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(0) AND NOT use_freezer/rom_bank_0 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$521)); FTCPE_use_freezer/rom_bank_1: FTCPE port map (use_freezer/rom_bank_1,use_freezer/rom_bank_1_T,NOT phi2short,'0','0'); use_freezer/rom_bank_1_T <= ((use_freezer/rom_bank_1 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(1) AND use_freezer/rom_bank_1 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(1) AND NOT use_freezer/rom_bank_1 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(1) AND NOT use_freezer/rom_bank_1 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(1) AND NOT use_freezer/rom_bank_1 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$521)); FTCPE_use_freezer/rom_bank_2: FTCPE port map (use_freezer/rom_bank_2,use_freezer/rom_bank_2_T,NOT phi2short,'0','0'); use_freezer/rom_bank_2_T <= ((NOT use_freezer/rom_bank_2 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(2) AND NOT use_freezer/rom_bank_2 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(2) AND use_freezer/rom_bank_2 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(2) AND use_freezer/rom_bank_2 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(2) AND use_freezer/rom_bank_2 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$521)); FTCPE_use_freezer/rom_bank_3: FTCPE port map (use_freezer/rom_bank_3,use_freezer/rom_bank_3_T,NOT phi2short,'0','0'); use_freezer/rom_bank_3_T <= ((NOT use_freezer/rom_bank_3 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(3) AND NOT use_freezer/rom_bank_3 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(3) AND use_freezer/rom_bank_3 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(3) AND use_freezer/rom_bank_3 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(3) AND use_freezer/rom_bank_3 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$521)); FTCPE_use_freezer/rom_bank_4: FTCPE port map (use_freezer/rom_bank_4,use_freezer/rom_bank_4_T,NOT phi2short,'0','0'); use_freezer/rom_bank_4_T <= ((NOT use_freezer/rom_bank_4 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(4) AND NOT use_freezer/rom_bank_4 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(4) AND use_freezer/rom_bank_4 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(4) AND use_freezer/rom_bank_4 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(4) AND use_freezer/rom_bank_4 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$521)); FTCPE_use_freezer/rom_bank_5: FTCPE port map (use_freezer/rom_bank_5,use_freezer/rom_bank_5_T,NOT phi2short,'0','0'); use_freezer/rom_bank_5_T <= ((NOT use_freezer/rom_bank_5 AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (a(9) AND a(8) AND a(10) AND a(6) AND a(5) AND NOT use_freezer/rom_bank_5 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(5) AND use_freezer/rom_bank_5 AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(5) AND use_freezer/rom_bank_5 AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_DC$521) OR (a(9) AND a(8) AND a(10) AND a(6) AND NOT a(5) AND use_freezer/rom_bank_5 AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$521)); FDCPE_use_freezer/state0: FDCPE port map (use_freezer/state(0),use_freezer/next_state_FSM_FFd3,NOT phi2,'0','0'); FDCPE_use_freezer/state1: FDCPE port map (use_freezer/state(1),use_freezer/next_state_FSM_FFd2,NOT phi2,'0','0'); FDCPE_use_freezer/state2: FDCPE port map (use_freezer/state(2),use_freezer/next_state_FSM_FFd1,NOT phi2,'0','0'); FTCPE_use_freezer/use_status_as_ram_address0: FTCPE port map (use_freezer/use_status_as_ram_address(0),use_freezer/use_status_as_ram_address_T(0),NOT phi2short,'0','0'); use_freezer/use_status_as_ram_address_T(0) <= ((use_freezer/use_status_as_ram_address(0) AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2) OR (NOT rw AND a(9) AND a(8) AND a(10) AND NOT a(6) AND NOT a(5) AND use_freezer/use_status_as_ram_address(0) AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2) OR (rw AND a(9) AND a(8) AND a(10) AND NOT a(6) AND NOT a(5) AND NOT use_freezer/use_status_as_ram_address(0) AND use_freezer/next_state_FSM_FFd1 AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2) OR (rw AND a(9) AND a(8) AND a(10) AND NOT a(6) AND NOT a(5) AND NOT use_freezer/use_status_as_ram_address(0) AND use_freezer/next_state_FSM_FFd3 AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2) OR (rw AND a(9) AND a(8) AND a(10) AND NOT a(6) AND NOT a(5) AND NOT use_freezer/use_status_as_ram_address(0) AND use_freezer/next_state_FSM_FFd2 AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2)); FDCPE_use_freezer/vector_a2: FDCPE port map (use_freezer/vector_a2,a(2),NOT phi2short,'0','0',use_freezer/vector_a2_CE); use_freezer/vector_a2_CE <= (a(14) AND a(15) AND rw AND a(11) AND a(6) AND a(5) AND a(13) AND a(4) AND a(3) AND NOT a(0) AND a(12) AND reset_n_sync(1) AND NOT use_freezer/next_state_FSM_FFd1 AND NOT use_freezer/next_state_FSM_FFd3 AND NOT use_freezer/next_state_FSM_FFd2 AND NOT activate_n_sync(1) AND $OpTx$FX_SC$586); FTCPE_use_pia/pia_crb2: FTCPE port map (use_pia/pia_crb2,use_pia/pia_crb2_T,NOT phi2short,'0','0'); use_pia/pia_crb2_T <= ((use_pia/pia_crb2 AND NOT reset_n_sync(1)) OR (NOT rw AND a(9) AND a(8) AND a(1) AND NOT a(2) AND NOT d(2).PIN AND NOT a(3) AND a(0) AND use_pia/pia_crb2 AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2) OR (NOT rw AND a(9) AND a(8) AND a(1) AND NOT a(2) AND d(2).PIN AND NOT a(3) AND a(0) AND NOT use_pia/pia_crb2 AND reset_n_sync(1) AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2)); FDCPE_use_pia/pia_ddrb2: FDCPE port map (use_pia/pia_ddrb(2),use_pia/pia_ddrb_D(2),NOT phi2short,'0','0'); use_pia/pia_ddrb_D(2) <= ((use_pia/pia_ddrb(2) AND NOT use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2) OR (d(2).PIN AND reset_n_sync(1) AND use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2)); FDCPE_use_pia/pia_ddrb3: FDCPE port map (use_pia/pia_ddrb(3),use_pia/pia_ddrb_D(3),NOT phi2short,'0','0'); use_pia/pia_ddrb_D(3) <= ((use_pia/pia_ddrb(3) AND NOT use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2) OR (d(3).PIN AND reset_n_sync(1) AND use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2)); FDCPE_use_pia/pia_ddrb4: FDCPE port map (use_pia/pia_ddrb(4),use_pia/pia_ddrb_D(4),NOT phi2short,'0','0'); use_pia/pia_ddrb_D(4) <= ((use_pia/pia_ddrb(4) AND NOT use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2) OR (d(4).PIN AND reset_n_sync(1) AND use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2)); FDCPE_use_pia/pia_ddrb5: FDCPE port map (use_pia/pia_ddrb(5),use_pia/pia_ddrb_D(5),NOT phi2short,'0','0'); use_pia/pia_ddrb_D(5) <= ((use_pia/pia_ddrb(5) AND NOT use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2) OR (d(5).PIN AND reset_n_sync(1) AND use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2)); FDCPE_use_pia/pia_ddrb6: FDCPE port map (use_pia/pia_ddrb(6),use_pia/pia_ddrb_D(6),NOT phi2short,'0','0'); use_pia/pia_ddrb_D(6) <= ((use_pia/pia_ddrb(6) AND NOT use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2) OR (reset_n_sync(1) AND d(6).PIN AND use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2)); FDCPE_use_pia/pia_ddrb7: FDCPE port map (use_pia/pia_ddrb(7),use_pia/pia_ddrb_D(7),NOT phi2short,'0','0'); use_pia/pia_ddrb_D(7) <= ((use_pia/pia_ddrb(7) AND NOT use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2) OR (reset_n_sync(1) AND d(7).PIN AND use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2)); use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2 <= ((NOT reset_n_sync(1)) OR (NOT rw AND a(9) AND a(8) AND NOT a(1) AND NOT a(2) AND NOT a(3) AND a(0) AND NOT use_pia/pia_crb2 AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2)); FDCPE_use_pia/pia_portb2: FDCPE port map (use_pia/pia_portb(2),use_pia/pia_portb_D(2),NOT phi2short,'0','0'); use_pia/pia_portb_D(2) <= ((use_pia/pia_portb(2) AND NOT use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2) OR (d(2).PIN AND reset_n_sync(1) AND use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2)); FDCPE_use_pia/pia_portb3: FDCPE port map (use_pia/pia_portb(3),use_pia/pia_portb_D(3),NOT phi2short,'0','0'); use_pia/pia_portb_D(3) <= ((use_pia/pia_portb(3) AND NOT use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2) OR (d(3).PIN AND reset_n_sync(1) AND use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2)); FDCPE_use_pia/pia_portb4: FDCPE port map (use_pia/pia_portb(4),use_pia/pia_portb_D(4),NOT phi2short,'0','0'); use_pia/pia_portb_D(4) <= ((use_pia/pia_portb(4) AND NOT use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2) OR (d(4).PIN AND reset_n_sync(1) AND use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2)); FDCPE_use_pia/pia_portb5: FDCPE port map (use_pia/pia_portb(5),use_pia/pia_portb_D(5),NOT phi2short,'0','0'); use_pia/pia_portb_D(5) <= ((use_pia/pia_portb(5) AND NOT use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2) OR (d(5).PIN AND reset_n_sync(1) AND use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2)); FDCPE_use_pia/pia_portb6: FDCPE port map (use_pia/pia_portb(6),use_pia/pia_portb_D(6),NOT phi2short,'0','0'); use_pia/pia_portb_D(6) <= ((use_pia/pia_portb(6) AND NOT use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2) OR (reset_n_sync(1) AND d(6).PIN AND use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2)); FDCPE_use_pia/pia_portb7: FDCPE port map (use_pia/pia_portb(7),use_pia/pia_portb_D(7),NOT phi2short,'0','0'); use_pia/pia_portb_D(7) <= ((use_pia/pia_portb(7) AND NOT use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2) OR (reset_n_sync(1) AND d(7).PIN AND use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2)); use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2 <= ((NOT reset_n_sync(1)) OR (NOT rw AND a(9) AND a(8) AND NOT a(1) AND NOT a(2) AND NOT a(3) AND a(0) AND use_pia/pia_crb2 AND $OpTx$FX_DC$508 AND $OpTx$FX_DC$521 AND NOT use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2)); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95144XL-10-TQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC95144XL-10-TQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 a<4> 51 VCC 2 extsel_in 52 PGND 3 a<5> 53 PGND 4 a<6> 54 PGND 5 VCC 55 PGND 6 a<7> 56 PGND 7 cartemu_enable_n 57 VCC 8 a<8> 58 PGND 9 a<9> 59 PGND 10 a<10> 60 PGND 11 a<11> 61 PGND 12 a<12> 62 GND 13 a<13> 63 PGND 14 a<14> 64 PGND 15 a<15> 65 PGND 16 d<0> 66 PGND 17 d<1> 67 PGND 18 d<2> 68 PGND 19 flash_we_n 69 GND 20 d<3> 70 PGND 21 GND 71 nc_adr<1> 22 phi2 72 nc_adr<2> 23 mpd_in 73 refresh 24 ramdisk_enable_n 74 nc_adr<3> 25 d<4> 75 GND 26 VCC 76 nc_adr<4> 27 phi2short 77 ram_rom_we 28 d<5> 78 ram_rom_oe 29 d<6> 79 rom0_ce 30 d<7> 80 PGND 31 GND 81 ram0_ce 32 PGND 82 ram_rom_a<12> 33 rw 83 TDO 34 dualpokey_n 84 GND 35 a<2> 85 ram_rom_a<13> 36 a<3> 86 ram_rom_a<14> 37 PGND 87 ram_rom_a<15> 38 VCC 88 VCC 39 PGND 89 ram_rom_a<16> 40 PGND 90 ram_rom_a<17> 41 PGND 91 ram_rom_a<18> 42 a<0> 92 ram_a<4> 43 oldos_n 93 ram_a<5> 44 GND 94 ram_a<6> 45 TDI 95 ram_a<7> 46 activate_n_in 96 ram1_ce 47 TMS 97 rom1_ce 48 TCK 98 VCC 49 irq_in 99 reset_n_in 50 a<1> 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95144xl-10-TQ100 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : ON Slew Rate : SLOW Power Mode : LOW Ground on Unused IOs : ON Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 18 Pterm Limit : 90