Logic

Signal Name Total Pterms Total Inputs Function Block Macrocell Power Mode Slew Rate Pin Number Pin Type Pin Use Reg Init State
N0/N0_TRST 10 18 FB6 MC7 LOW     (b) (b)  
$OpTx$BIN_STEP$742 10 17 FB3 MC18 LOW     (b) (b)  
$OpTx$FX_DC$484 1 3 FB4 MC7 LOW     (b) (b)  
$OpTx$FX_DC$493 1 3 FB3 MC1 LOW     (b) (b)  
$OpTx$FX_DC$495 3 13 FB1 MC5 LOW   13 I/O I  
$OpTx$FX_DC$506 1 6 FB4 MC4 LOW     (b) (b)  
$OpTx$FX_DC$507 1 2 FB6 MC18 LOW     (b) (b)  
$OpTx$FX_DC$523 3 8 FB4 MC16 LOW     (b) (b)  
$OpTx$FX_DC$525 3 5 FB7 MC18 LOW     (b) (b)  
$OpTx$FX_DC$555 3 6 FB2 MC17 LOW   10 I/O I  
$OpTx$FX_DC$561 3 6 FB2 MC16 LOW     (b) (b)  
$OpTx$FX_DC$564 1 7 FB5 MC2 LOW   35 I/O I  
$OpTx$FX_DC$585 2 4 FB6 MC13 LOW     (b) (b)  
$OpTx$FX_DC$592 2 5 FB7 MC17 LOW   61 I/O (b)  
$OpTx$FX_SC$570 1 4 FB4 MC3 LOW     (b) (b)  
$OpTx$FX_SC$574 1 8 FB4 MC1 LOW     (b) (b)  
$OpTx$INV$475 6 10 FB8 MC16 LOW     (b) (b)  
activate_n_sync<0> 1 1 FB7 MC11 LOW   56 I/O (b) RESET
activate_n_sync<1> 1 1 FB7 MC10 LOW     (b) (b) RESET
d<0> 4 10 FB1 MC9 LOW SLOW 16 I/O I/O  
d<1> 7 17 FB1 MC11 LOW SLOW 17 I/O I/O  
d<2> 6 16 FB1 MC12 LOW SLOW 18 I/O I/O  
d<3> 5 17 FB1 MC15 LOW SLOW 20 I/O I/O  
d<4> 5 17 FB3 MC6 LOW SLOW 25 I/O I/O  
d<5> 6 18 FB3 MC9 LOW SLOW 28 I/O I/O  
d<6> 4 16 FB3 MC11 LOW SLOW 29 I/O I/O  
d<7> 2 6 FB3 MC12 LOW SLOW 30 I/O I/O  
dout_enable 7 16 FB1 MC16 LOW     (b) (b)  
freezer_mem_dout<5>/freezer_mem_dout<5>_D2 2 18 FB4 MC13 LOW     (b) (b)  
merged_out_dout_or0000/merged_out_dout_or0000_D2 6 13 FB4 MC18 LOW     (b) (b)  
powerup_n 1 3 FB7 MC9 LOW   55 I/O (b) RESET
ram_a<4> 8 16 FB4 MC9 LOW SLOW 92 I/O O  
ram_a<5> 6 11 FB4 MC11 LOW SLOW 93 I/O O  
ram_a<6> 4 9 FB4 MC12 LOW SLOW 94 I/O O  
ram_a<7> 4 9 FB4 MC14 LOW SLOW 95 I/O O  
ram_ce 5 14 FB6 MC12 LOW SLOW 81 I/O O  
ram_rom_a<12> 12 17 FB6 MC14 LOW SLOW 82 I/O O  
ram_rom_a<13> 8 18 FB6 MC15 LOW SLOW 85 I/O O  
ram_rom_a<14> 6 11 FB6 MC17 LOW SLOW 86 I/O O  
ram_rom_a<15> 6 11 FB4 MC2 LOW SLOW 87 I/O O  
ram_rom_a<16> 6 11 FB4 MC5 LOW SLOW 89 I/O O  
ram_rom_a<17> 8 14 FB4 MC6 LOW SLOW 90 I/O O  
ram_rom_a<18> 7 13 FB4 MC8 LOW SLOW 91 I/O O  
ram_rom_a<19> 4 9 FB4 MC15 LOW SLOW 96 I/O O  
ram_rom_oe 1 2 FB6 MC8 LOW SLOW 78 I/O O  
ram_rom_we 1 2 FB6 MC6 LOW SLOW 77 I/O O  
ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2 1 5 FB7 MC8 LOW   54 I/O (b)  
refresh 1 1 FB8 MC17 LOW SLOW 73 I/O O  
reset_n_sync<0> 1 1 FB7 MC7 LOW     (b) (b) RESET
reset_n_sync<1> 1 1 FB7 MC6 LOW   53 I/O (b) RESET
reset_n_sync<2> 1 1 FB7 MC5 LOW   52 I/O (b) RESET
reset_n_sync<3> 1 1 FB7 MC4 LOW     (b) (b) RESET
rom0_ce 4 10 FB6 MC9 LOW SLOW 79 I/O O  
rom1_ce 5 12 FB4 MC17 LOW SLOW 97 I/O O  
use_cartemu/N29/use_cartemu/N29_D2 3 6 FB6 MC11 LOW   80 I/O (b)  
use_cartemu/N4/use_cartemu/N4_D2 1 8 FB2 MC1 LOW     (b) (b)  
use_cartemu/N50/use_cartemu/N50_D2 9 15 FB8 MC18 LOW     (b) (b)  
use_cartemu/N97/use_cartemu/N97_D2 2 10 FB3 MC4 LOW     (b) (b)  
use_cartemu/SFDecomp_100/use_cartemu/SFDecomp_100_D2 2 4 FB2 MC10 LOW     (b) (b)  
use_cartemu/address_14_mux0003/use_cartemu/address_14_mux0003_D2 3 6 FB2 MC15 LOW   9 I/O I  
use_cartemu/address_15_mux0003/use_cartemu/address_15_mux0003_D2 3 6 FB2 MC14 LOW   8 I/O I  
use_cartemu/address_18_mux0003/use_cartemu/address_18_mux0003_D2 3 6 FB2 MC13 LOW     (b) (b)  
use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2 2 3 FB3 MC3 LOW     (b) (b)  
use_cartemu/cart_disable_atari/use_cartemu/cart_disable_atari_D2 7 12 FB6 MC10 LOW     (b) (b)  
use_cartemu/cctl_dout_and0000/use_cartemu/cctl_dout_and0000_D2 2 10 FB6 MC16 LOW     (b) (b)  
use_cartemu/cfg_bank<0> 4 16 FB1 MC14 LOW   19 I/O I RESET
use_cartemu/cfg_bank<1> 4 16 FB1 MC13 LOW     (b) (b) RESET
use_cartemu/cfg_bank<2> 4 16 FB1 MC10 LOW     (b) (b) RESET
use_cartemu/cfg_bank<3> 4 16 FB1 MC8 LOW   15 I/O I RESET
use_cartemu/cfg_bank<4> 4 17 FB1 MC7 LOW     (b) (b) RESET
use_cartemu/cfg_bank<5> 4 17 FB1 MC6 LOW   14 I/O I RESET
use_cartemu/cfg_bank<6> 4 15 FB3 MC10 LOW     (b) (b) RESET
use_cartemu/cfg_enable 17 16 FB1 MC2 LOW   11 I/O I RESET
use_cartemu/cfg_menu 4 13 FB8 MC10 LOW     (b) (b) RESET
use_cartemu/cfg_mode<0> 3 12 FB1 MC4 LOW     (b) (b) RESET
use_cartemu/cfg_mode<1> 3 12 FB8 MC8 LOW   66 I/O (b) RESET
use_cartemu/cfg_mode<2> 3 12 FB8 MC7 LOW     (b) (b) RESET
use_cartemu/cfg_source_ram 3 12 FB8 MC6 LOW   65 I/O (b) RESET
use_cartemu/cfg_sram_bank<0> 2 3 FB7 MC16 LOW     (b) (b) RESET
use_cartemu/cfg_sram_bank<1> 2 3 FB2 MC9 LOW   4 I/O/GTS2 I RESET
use_cartemu/cfg_sram_bank<2> 2 3 FB2 MC8 LOW   3 I/O/GTS1 I RESET
use_cartemu/cfg_sram_bank<3> 2 3 FB2 MC7 LOW     (b) (b) RESET
use_cartemu/cfg_sram_bank<4> 2 3 FB7 MC15 LOW   60 I/O (b) RESET
use_cartemu/cfg_sram_bank<5> 2 3 FB2 MC6 LOW   2 I/O/GTS4 I RESET
use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2 1 9 FB1 MC3 LOW   12 I/O I  
use_cartemu/cfg_sram_enable 4 11 FB8 MC9 LOW   67 I/O (b) RESET
use_cartemu/cfg_usdx<0> 3 12 FB8 MC5 LOW   64 I/O (b) RESET
use_cartemu/cfg_usdx<1> 3 12 FB8 MC4 LOW     (b) (b) RESET
use_cartemu/cfg_write_enable 8 15 FB1 MC18 LOW     (b) (b) RESET
use_cartemu/do_access_mux0005/use_cartemu/do_access_mux0005_D2 8 17 FB2 MC18 LOW     (b) (b)  
use_cartemu/oss_bank<0> 2 8 FB5 MC15 LOW   46 I/O I RESET
use_cartemu/oss_bank<1> 2 8 FB5 MC14 LOW   43 I/O I RESET
use_cartemu/trig3_disable_atari 5 18 FB8 MC15 LOW   72 I/O I  
use_cartemu/usdx_bank<0> 2 6 FB5 MC13 LOW     (b) (b) RESET
use_cartemu/usdx_bank<1> 2 6 FB2 MC5 LOW   1 I/O/GTS3 I RESET
use_cartemu/usdx_bank<2> 2 6 FB2 MC4 LOW     (b) (b) RESET
use_cartemu/usdx_bank<3> 2 6 FB2 MC3 LOW     (b) (b) RESET
use_cartemu/usdx_bank<4> 2 6 FB5 MC12 LOW   42 I/O I RESET
use_cartemu/usdx_bank<5> 2 6 FB2 MC2 LOW   99 I/O/GSR I RESET
use_cartemu/usdx_ctl<0> 3 7 FB2 MC12 LOW   7 I/O I RESET
use_cartemu/usdx_ctl<1> 3 7 FB2 MC11 LOW   6 I/O I RESET
use_freezer/N24/use_freezer/N24_D2 2 5 FB4 MC10 LOW     (b) (b)  
use_freezer/next_state_FSM_FFd1 3 6 FB3 MC8 LOW   27 I/O/GCK3 GCK/I RESET
use_freezer/next_state_FSM_FFd2 3 18 FB3 MC7 LOW     (b) (b) RESET
use_freezer/next_state_FSM_FFd3 3 18 FB3 MC5 LOW   24 I/O I RESET
use_freezer/next_state_cmp_eq0001/use_freezer/next_state_cmp_eq0001_D2 1 5 FB5 MC1 LOW     (b) (b)  
use_freezer/ram_bank_0 5 13 FB3 MC17 LOW   34 I/O I RESET
use_freezer/ram_bank_1 5 13 FB3 MC16 LOW     (b) (b) RESET
use_freezer/ram_bank_2 5 13 FB3 MC15 LOW   33 I/O I RESET
use_freezer/ram_bank_3 5 13 FB3 MC14 LOW   32 I/O (b) RESET
use_freezer/ram_bank_4 5 13 FB3 MC13 LOW     (b) (b) RESET
use_freezer/rom_bank_0 5 10 FB8 MC14 LOW   71 I/O I RESET
use_freezer/rom_bank_1 5 10 FB8 MC13 LOW     (b) (b) RESET
use_freezer/rom_bank_2 5 10 FB8 MC12 LOW   70 I/O (b) RESET
use_freezer/rom_bank_3 5 10 FB5 MC18 LOW     (b) (b) RESET
use_freezer/rom_bank_4 5 10 FB5 MC17 LOW   49 I/O I RESET
use_freezer/rom_bank_5 5 10 FB5 MC16 LOW     (b) (b) RESET
use_freezer/state<0> 1 1 FB7 MC3 LOW     (b) (b) RESET
use_freezer/state<1> 1 1 FB7 MC2 LOW   50 I/O I RESET
use_freezer/state<2> 1 1 FB7 MC1 LOW     (b) (b) RESET
use_freezer/use_status_as_ram_address<0> 5 12 FB8 MC11 LOW   68 I/O (b) RESET
use_freezer/vector_a2 2 18 FB3 MC2 LOW   23 I/O/GCK2 I RESET
use_pia/pia_crb2 3 13 FB8 MC3 LOW     (b) (b) RESET
use_pia/pia_ddrb<2> 2 4 FB5 MC11 LOW   41 I/O (b) RESET
use_pia/pia_ddrb<3> 2 4 FB5 MC10 LOW     (b) (b) RESET
use_pia/pia_ddrb<4> 2 4 FB5 MC9 LOW   40 I/O (b) RESET
use_pia/pia_ddrb<5> 2 4 FB5 MC8 LOW   39 I/O (b) RESET
use_pia/pia_ddrb<6> 2 4 FB5 MC7 LOW     (b) (b) RESET
use_pia/pia_ddrb<7> 2 4 FB5 MC6 LOW   37 I/O (b) RESET
use_pia/pia_ddrb_0__or0000/use_pia/pia_ddrb_0__or0000_D2 2 12 FB8 MC2 LOW   63 I/O (b)  
use_pia/pia_portb<2> 2 4 FB5 MC5 LOW   36 I/O I RESET
use_pia/pia_portb<3> 2 4 FB5 MC4 LOW     (b) (b) RESET
use_pia/pia_portb<4> 2 4 FB5 MC3 LOW     (b) (b) RESET
use_pia/pia_portb<5> 2 4 FB7 MC14 LOW   59 I/O (b) RESET
use_pia/pia_portb<6> 2 4 FB7 MC13 LOW     (b) (b) RESET
use_pia/pia_portb<7> 2 4 FB7 MC12 LOW   58 I/O (b) RESET
use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2 2 12 FB8 MC1 LOW     (b) (b)