Signal Name Total Product Terms Product Terms Location Power Mode Pin Number PinType Pin Use
use_freezer/state<2> 1  1_1 MC1 LOW   (b) (b)
use_freezer/state<1> 1  2_1 MC2 LOW 50 I/O I
use_freezer/state<0> 1  3_1 MC3 LOW   (b) (b)
reset_n_sync<3> 1  4_1 MC4 LOW   (b) (b)
reset_n_sync<2> 1  5_1 MC5 LOW 52 I/O (b)
reset_n_sync<1> 1  6_1 MC6 LOW 53 I/O (b)
reset_n_sync<0> 1  7_1 MC7 LOW   (b) (b)
ramdisk_mem_adr<19>/ramdisk_mem_adr<19>_D2 1  8_1 MC8 LOW 54 I/O (b)
powerup_n 1  9_1  MC9 LOW 55 I/O (b)
activate_n_sync<1> 1  10_1 MC10 LOW   (b) (b)
activate_n_sync<0> 1  11_1 MC11 LOW 56 I/O (b)
use_pia/pia_portb<7> 2  12_1 12_2 MC12 LOW 58 I/O (b)
use_pia/pia_portb<6> 2  13_1 13_2 MC13 LOW   (b) (b)
use_pia/pia_portb<5> 2  14_1 14_2 MC14 LOW 59 I/O (b)
use_cartemu/cfg_sram_bank<4> 2  15_1 15_2 MC15 LOW 60 I/O (b)
use_cartemu/cfg_sram_bank<0> 2  16_1 16_2 MC16 LOW   (b) (b)
$OpTx$FX_DC$592 2  17_1 17_2 MC17 LOW 61 I/O (b)
$OpTx$FX_DC$525 3  18_1 18_2 18_3 MC18 LOW   (b) (b)

Signals Used By Logic in Function Block
  1. d<7>.PIN
  2. d<6>.PIN
  3. d<5>.PIN
  4. d<4>.PIN
  5. d<0>.PIN
  6. a<14>
  7. a<15>
  8. activate_n_in
  9. activate_n_sync<0>
  10. powerup_n
  11. ramdisk_enable_n
  12. reset_n_in
  13. reset_n_sync<0>
  14. reset_n_sync<1>
  15. reset_n_sync<2>
  16. reset_n_sync<3>
  17. use_cartemu/N29/use_cartemu/N29_D2
  18. use_cartemu/N4/use_cartemu/N4_D2
  19. use_cartemu/address_19_and0000/use_cartemu/address_19_and0000_D2
  20. use_cartemu/cfg_bank<4>
  21. use_cartemu/cfg_sram_bank<0>
  22. use_cartemu/cfg_sram_bank<4>
  23. use_cartemu/cfg_sram_bank_not0001/use_cartemu/cfg_sram_bank_not0001_D2
  24. use_cartemu/usdx_bank<0>
  25. use_cartemu/usdx_bank<4>
  26. use_freezer/next_state_FSM_FFd1
  27. use_freezer/next_state_FSM_FFd2
  28. use_freezer/next_state_FSM_FFd3
  29. use_pia/pia_ddrb<4>
  30. use_pia/pia_portb<4>
  31. use_pia/pia_portb<5>
  32. use_pia/pia_portb<6>
  33. use_pia/pia_portb<7>
  34. use_pia/pia_portb_0__or0000/use_pia/pia_portb_0__or0000_D2