Timing Report

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Design Name TheCart
Device, Speed (SpeedFile Version) XC95144XL, -10 (3.0)
Date Created Sun Feb 9 23:42:51 2014
Created By Timing Report Generator: version M.81d
Copyright Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.

Summary

Performance Summary
Min. Clock Period 55.100 ns.
Max. Clock Frequency (fSYSTEM) 18.149 MHz.
Limited by Cycle Time for phi2short
Clock to Setup (tCYC) 55.100 ns.
Pad to Pad Delay (tPD) 48.800 ns.
Setup to Clock at the Pad (tSU) 51.600 ns.
Clock Pad to Output Pad Delay (tCO) 66.100 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS_phi_we 20.0 20.0 1 0
TS_phi_oe 20.0 20.0 1 0
TS_phi2short 560.0 55.1 221 0


Constraint: TS_phi_we

Description: FROM:phi2short:TO:ram_rom_we:20.000nS
Path Requirement (ns) Delay (ns) Slack (ns)
phi2short to ram_rom_we 20.000 20.000 0.000


Constraint: TS_phi_oe

Description: FROM:phi2:TO:ram_rom_oe:20.000nS
Path Requirement (ns) Delay (ns) Slack (ns)
phi2 to ram_rom_oe 20.000 20.000 0.000


Constraint: TS_phi2short

Description: PERIOD:phi2short:560.000nS:HIGH:280.000nS
Path Requirement (ns) Delay (ns) Slack (ns)
mod_en.Q to cfg_bank<16>.D 560.000 55.100 504.900
mod_en.Q to cfg_bank<17>.D 560.000 55.100 504.900
mod_en.Q to cfg_bank<18>.D 560.000 55.100 504.900



Number of constraints not met: 0

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
phi2short 18.149 Limited by Cycle Time for phi2short

Setup/Hold Times for Clocks

Setup/Hold Times for Clock phi2short
Source Pad Setup to clk (edge) Hold to clk (edge)
adr<0> 38.400 0.000
adr<1> 38.400 0.000
adr<2> 38.400 0.000
adr<3> 39.400 0.000
adr<4> 51.600 0.000
adr<5> 51.600 0.000
adr<6> 51.600 0.000
adr<7> 51.600 0.000
cctl 39.400 0.000
data<0> 13.400 0.000
data<1> 13.400 0.000
data<2> 13.400 0.000
data<3> 13.400 0.000
data<4> 13.400 0.000
data<5> 13.400 0.000
data<6> 13.000 0.000
data<7> 13.400 0.000
reset_n 12.000 0.000
rw 39.400 0.000


Clock to Pad Timing

Clock phi2short to Pad
Destination Pad Clock (edge) to Pad
ram_ce 66.100
rom_ce 65.100
data<0> 55.500
data<1> 55.500
data<2> 55.500
data<3> 55.500
data<4> 55.500
data<5> 55.500
data<6> 55.500
data<7> 55.500
ram_rom_adr<14> 50.900
ram_rom_adr<15> 50.900
ram_rom_adr<19> 50.900
ram_rom_adr<22> 50.900
ram_rom_adr<24> 50.900
ram_rom_adr<26> 50.900
ram_rom_adr<16> 49.900
ram_rom_adr<17> 49.900
ram_rom_adr<18> 49.900
ram_rom_adr<20> 49.900
ram_rom_adr<21> 49.900
ram_rom_adr<23> 49.900
ram_rom_adr<25> 49.900
ram_rom_adr<12> 37.700
ram_rom_adr<13> 37.700
rd4 37.700
rd5 37.700
eeprom_cs 10.300
eeprom_sck 10.300
eeprom_si 10.300
mod_en 10.300
rom_reset 10.300


Clock to Setup Times for Clocks

Clock to Setup for clock phi2short
Source Destination Delay
mod_en.Q cfg_bank<16>.D 55.100
mod_en.Q cfg_bank<17>.D 55.100
mod_en.Q cfg_bank<18>.D 55.100
cfg_mode<0>.Q use_cart_logic/oss_bank<0>.D 42.900
cfg_mode<0>.Q use_cart_logic/oss_bank<1>.D 42.900
cfg_mode<1>.Q use_cart_logic/oss_bank<0>.D 42.900
cfg_mode<1>.Q use_cart_logic/oss_bank<1>.D 42.900
mod_en.Q cfg_bank2<13>.D 42.900
mod_en.Q cfg_mode<0>.D 42.900
mod_en.Q use_cart_logic/oss_bank<0>.D 42.900
mod_en.Q use_cart_logic/oss_bank<1>.D 42.900
cfg_mode<0>.Q sic_8xxx_enable.D 41.900
cfg_mode<0>.Q sic_axxx_enable.D 41.900
cfg_mode<1>.Q cfg_bank<14>.D 41.900
cfg_mode<1>.Q cfg_bank<15>.D 41.900
cfg_mode<1>.Q sic_8xxx_enable.D 41.900
cfg_mode<1>.Q sic_axxx_enable.D 41.900
cfg_mode<2>.Q cfg_bank<14>.D 41.900
cfg_mode<2>.Q cfg_bank<15>.D 41.900
mod_en.Q cfg_bank2<14>.D 41.900
mod_en.Q cfg_bank2<15>.D 41.900
mod_en.Q cfg_bank2<16>.D 41.900
mod_en.Q cfg_bank2<17>.D 41.900
mod_en.Q cfg_bank2<18>.D 41.900
mod_en.Q cfg_bank2<19>.D 41.900
mod_en.Q cfg_bank2<20>.D 41.900
mod_en.Q cfg_bank2<21>.D 41.900
mod_en.Q cfg_bank2<22>.D 41.900
mod_en.Q cfg_bank2<23>.D 41.900
mod_en.Q cfg_bank2<24>.D 41.900
mod_en.Q cfg_bank2<25>.D 41.900
mod_en.Q cfg_bank2<26>.D 41.900
mod_en.Q cfg_bank<13>.D 41.900
mod_en.Q cfg_bank<14>.D 41.900
mod_en.Q cfg_bank<15>.D 41.900
mod_en.Q cfg_bank<19>.D 41.900
mod_en.Q cfg_bank<20>.D 41.900
mod_en.Q cfg_bank<21>.D 41.900
mod_en.Q cfg_bank<22>.D 41.900
mod_en.Q cfg_bank<23>.D 41.900
mod_en.Q cfg_bank<24>.D 41.900
mod_en.Q cfg_bank<25>.D 41.900
mod_en.Q cfg_bank<26>.D 41.900
mod_en.Q cfg_mode<1>.D 41.900
mod_en.Q cfg_mode<2>.D 41.900
mod_en.Q cfg_mode<3>.D 41.900
mod_en.Q cfg_mode<4>.D 41.900
mod_en.Q cfg_mode<5>.D 41.900
mod_en.Q cfg_source_ram.D 41.900
mod_en.Q cfg_source_ram2.D 41.900
mod_en.Q cfg_write_enable.D 41.900
mod_en.Q cfg_write_enable2.D 41.900
cfg_mode<0>.Q cfg_enable.D 31.100
cfg_mode<2>.Q cfg_enable.D 31.100
cfg_mode<3>.Q cfg_enable.D 31.100
mod_en.Q eeprom_si.D 30.700
cfg_mode<5>.Q cfg_enable.D 30.500
mod_en.Q cfg_enable.D 30.500
cfg_mode<0>.Q cfg_bank<13>.D 30.100
cfg_mode<0>.Q cfg_bank<14>.D 30.100
cfg_mode<1>.Q cfg_bank<13>.D 30.100
cfg_mode<1>.Q cfg_enable.D 30.100
cfg_mode<2>.Q cfg_bank<13>.D 30.100
cfg_mode<0>.Q cfg_bank<15>.D 29.700
cfg_mode<0>.Q cfg_bank<16>.D 29.700
cfg_mode<0>.Q cfg_bank<17>.D 29.700
cfg_mode<0>.Q cfg_bank<18>.D 29.700
cfg_mode<1>.Q cfg_bank<18>.D 29.700
cfg_mode<2>.Q cfg_bank<16>.D 29.700
cfg_mode<2>.Q cfg_bank<17>.D 29.700
cfg_mode<2>.Q cfg_bank<18>.D 29.700
cfg_mode<2>.Q use_cart_logic/oss_bank<0>.D 29.700
cfg_mode<2>.Q use_cart_logic/oss_bank<1>.D 29.700
cfg_mode<3>.Q cfg_bank<13>.D 29.700
cfg_mode<3>.Q cfg_bank<14>.D 29.700
cfg_mode<3>.Q cfg_bank<15>.D 29.700
cfg_mode<3>.Q cfg_bank<16>.D 29.700
cfg_mode<3>.Q cfg_bank<17>.D 29.700
cfg_mode<3>.Q cfg_bank<18>.D 29.700
cfg_mode<3>.Q use_cart_logic/oss_bank<0>.D 29.700
cfg_mode<3>.Q use_cart_logic/oss_bank<1>.D 29.700
cfg_mode<4>.Q cfg_bank<14>.D 29.700
cfg_mode<4>.Q cfg_bank<15>.D 29.700
cfg_mode<4>.Q cfg_bank<16>.D 29.700
cfg_mode<4>.Q cfg_bank<17>.D 29.700
cfg_mode<4>.Q cfg_bank<18>.D 29.700
cfg_mode<4>.Q use_cart_logic/oss_bank<0>.D 29.700
cfg_mode<4>.Q use_cart_logic/oss_bank<1>.D 29.700
cfg_mode<5>.Q cfg_bank<14>.D 29.700
cfg_mode<5>.Q cfg_bank<15>.D 29.700
cfg_mode<5>.Q cfg_bank<16>.D 29.700
cfg_mode<5>.Q cfg_bank<17>.D 29.700
cfg_mode<5>.Q cfg_bank<18>.D 29.700
cfg_mode<5>.Q use_cart_logic/oss_bank<0>.D 29.700
cfg_mode<5>.Q use_cart_logic/oss_bank<1>.D 29.700
mod_en.Q cfg_enable2.D 29.700
mod_en.Q eeprom_cs.D 29.700
mod_en.Q eeprom_sck.D 29.700
reset_n_sync.Q cfg_bank2<13>.D 29.700
reset_n_sync.Q cfg_bank<16>.D 29.700
reset_n_sync.Q cfg_bank<17>.D 29.700
reset_n_sync.Q cfg_bank<18>.D 29.700
reset_n_sync.Q cfg_mode<0>.D 29.700
reset_n_sync.Q eeprom_si.D 29.700
cfg_mode<1>.Q cfg_bank<16>.D 28.700
cfg_mode<1>.Q cfg_bank<17>.D 28.700
cfg_mode<1>.Q cfg_bank<20>.D 28.700
cfg_mode<2>.Q sic_8xxx_enable.D 28.700
cfg_mode<2>.Q sic_axxx_enable.D 28.700
cfg_mode<3>.Q sic_8xxx_enable.D 28.700
cfg_mode<3>.Q sic_axxx_enable.D 28.700
cfg_mode<4>.Q cfg_bank<20>.D 28.700
cfg_mode<4>.Q sic_8xxx_enable.D 28.700
cfg_mode<4>.Q sic_axxx_enable.D 28.700
cfg_mode<5>.Q sic_8xxx_enable.D 28.700
cfg_mode<5>.Q sic_axxx_enable.D 28.700
reset_n_sync.Q cfg_bank2<14>.D 28.700
reset_n_sync.Q cfg_bank2<15>.D 28.700
reset_n_sync.Q cfg_bank2<16>.D 28.700
reset_n_sync.Q cfg_bank2<17>.D 28.700
reset_n_sync.Q cfg_bank2<18>.D 28.700
reset_n_sync.Q cfg_bank2<19>.D 28.700
reset_n_sync.Q cfg_bank2<20>.D 28.700
reset_n_sync.Q cfg_bank2<21>.D 28.700
reset_n_sync.Q cfg_bank2<22>.D 28.700
reset_n_sync.Q cfg_bank2<23>.D 28.700
reset_n_sync.Q cfg_bank2<24>.D 28.700
reset_n_sync.Q cfg_bank2<25>.D 28.700
reset_n_sync.Q cfg_bank2<26>.D 28.700
reset_n_sync.Q cfg_bank<21>.D 28.700
reset_n_sync.Q cfg_bank<22>.D 28.700
reset_n_sync.Q cfg_bank<23>.D 28.700
reset_n_sync.Q cfg_bank<24>.D 28.700
reset_n_sync.Q cfg_bank<25>.D 28.700
reset_n_sync.Q cfg_bank<26>.D 28.700
reset_n_sync.Q cfg_mode<1>.D 28.700
reset_n_sync.Q cfg_mode<2>.D 28.700
reset_n_sync.Q cfg_mode<3>.D 28.700
reset_n_sync.Q cfg_mode<4>.D 28.700
reset_n_sync.Q cfg_mode<5>.D 28.700
reset_n_sync.Q cfg_source_ram.D 28.700
reset_n_sync.Q cfg_source_ram2.D 28.700
reset_n_sync.Q cfg_write_enable.D 28.700
reset_n_sync.Q cfg_write_enable2.D 28.700
reset_n_sync.Q eeprom_cs.D 28.700
reset_n_sync.Q eeprom_sck.D 28.700
cfg_mode<4>.Q cfg_bank<13>.D 17.300
cfg_mode<4>.Q cfg_enable.D 17.300
cfg_mode<5>.Q cfg_bank<13>.D 17.300
reset_n_sync.Q cfg_bank<13>.D 17.300
cfg_bank<13>.Q cfg_bank<13>.D 16.900
cfg_enable.Q cfg_enable.D 16.900
cfg_mode<0>.Q cfg_bank<19>.D 16.900
cfg_mode<1>.Q cfg_bank<19>.D 16.900
cfg_mode<2>.Q cfg_bank<19>.D 16.900
cfg_mode<3>.Q cfg_bank<19>.D 16.900
cfg_mode<4>.Q cfg_bank<19>.D 16.900
cfg_mode<5>.Q cfg_bank<19>.D 16.900
reset_n_sync.Q cfg_bank<14>.D 16.900
reset_n_sync.Q cfg_bank<15>.D 16.900
reset_n_sync.Q cfg_bank<19>.D 16.900
cfg_bank<14>.Q cfg_bank<14>.D 16.500
cfg_bank<15>.Q cfg_bank<15>.D 16.500
cfg_bank<16>.Q cfg_bank<16>.D 16.500
cfg_bank<17>.Q cfg_bank<17>.D 16.500
cfg_bank<18>.Q cfg_bank<18>.D 16.500
cfg_bank<19>.Q cfg_bank<19>.D 16.500
cfg_bank<20>.Q cfg_bank<20>.D 16.500
cfg_enable2.Q cfg_enable2.D 16.500
cfg_mode<0>.Q cfg_bank<20>.D 16.500
cfg_mode<0>.Q cfg_mode<0>.D 16.500
cfg_mode<2>.Q cfg_bank<20>.D 16.500
cfg_mode<3>.Q cfg_bank<20>.D 16.500
cfg_mode<5>.Q cfg_bank<20>.D 16.500
eeprom_si.Q eeprom_si.D 16.500
reset_n_sync.Q cfg_bank<20>.D 16.500
reset_n_sync.Q cfg_enable.D 16.500
reset_n_sync.Q cfg_enable2.D 16.500
cfg_bank2<13>.Q cfg_bank2<13>.D 15.500
cfg_bank2<14>.Q cfg_bank2<14>.D 15.500
cfg_bank2<15>.Q cfg_bank2<15>.D 15.500
cfg_bank2<16>.Q cfg_bank2<16>.D 15.500
cfg_bank2<17>.Q cfg_bank2<17>.D 15.500
cfg_bank2<18>.Q cfg_bank2<18>.D 15.500
cfg_bank2<19>.Q cfg_bank2<19>.D 15.500
cfg_bank2<20>.Q cfg_bank2<20>.D 15.500
cfg_bank2<21>.Q cfg_bank2<21>.D 15.500
cfg_bank2<22>.Q cfg_bank2<22>.D 15.500
cfg_bank2<23>.Q cfg_bank2<23>.D 15.500
cfg_bank2<24>.Q cfg_bank2<24>.D 15.500
cfg_bank2<25>.Q cfg_bank2<25>.D 15.500
cfg_bank2<26>.Q cfg_bank2<26>.D 15.500
cfg_bank<21>.Q cfg_bank<21>.D 15.500
cfg_bank<22>.Q cfg_bank<22>.D 15.500
cfg_bank<23>.Q cfg_bank<23>.D 15.500
cfg_bank<24>.Q cfg_bank<24>.D 15.500
cfg_bank<25>.Q cfg_bank<25>.D 15.500
cfg_bank<26>.Q cfg_bank<26>.D 15.500
cfg_mode<1>.Q cfg_mode<1>.D 15.500
cfg_mode<2>.Q cfg_mode<2>.D 15.500
cfg_mode<3>.Q cfg_mode<3>.D 15.500
cfg_mode<4>.Q cfg_mode<4>.D 15.500
cfg_mode<5>.Q cfg_mode<5>.D 15.500
cfg_source_ram.Q cfg_source_ram.D 15.500
cfg_source_ram2.Q cfg_source_ram2.D 15.500
cfg_write_enable.Q cfg_write_enable.D 15.500
cfg_write_enable2.Q cfg_write_enable2.D 15.500
eeprom_cs.Q eeprom_cs.D 15.500
eeprom_sck.Q eeprom_sck.D 15.500
mod_en.Q mod_en.D 15.500
reset_n_sync.Q mod_en.D 15.500
reset_n_sync.Q sic_8xxx_enable.D 15.500
reset_n_sync.Q sic_axxx_enable.D 15.500
reset_n_sync.Q use_cart_logic/oss_bank<0>.D 15.500
reset_n_sync.Q use_cart_logic/oss_bank<1>.D 15.500
reset_n_sync1.Q reset_n_sync.D 15.500
sic_8xxx_enable.Q sic_8xxx_enable.D 15.500
sic_axxx_enable.Q sic_axxx_enable.D 15.500
use_cart_logic/oss_bank<0>.Q use_cart_logic/oss_bank<0>.D 15.500
use_cart_logic/oss_bank<1>.Q use_cart_logic/oss_bank<1>.D 15.500
reset_n_sync.Q rom_reset.CE 10.000


Pad to Pad List

Source Pad Destination Pad Delay
s4 ram_ce 48.800
s5 ram_ce 48.800
s4 rom_ce 47.800
s5 rom_ce 47.800
s4 data<0> 38.800
s4 data<1> 38.800
s4 data<2> 38.800
s4 data<3> 38.800
s4 data<4> 38.800
s4 data<5> 38.800
s4 data<6> 38.800
s4 data<7> 38.800
s5 data<0> 38.800
s5 data<1> 38.800
s5 data<2> 38.800
s5 data<3> 38.800
s5 data<4> 38.800
s5 data<5> 38.800
s5 data<6> 38.800
s5 data<7> 38.800
rw ram_ce 35.200
adr<0> data<0> 34.200
adr<0> data<1> 34.200
adr<0> data<2> 34.200
adr<0> data<3> 34.200
adr<0> data<4> 34.200
adr<0> data<5> 34.200
adr<0> data<7> 34.200
adr<1> data<0> 34.200
adr<1> data<1> 34.200
adr<1> data<2> 34.200
adr<1> data<3> 34.200
adr<1> data<4> 34.200
adr<1> data<5> 34.200
adr<1> data<7> 34.200
adr<2> data<0> 34.200
adr<2> data<1> 34.200
adr<2> data<2> 34.200
adr<2> data<3> 34.200
adr<2> data<4> 34.200
adr<2> data<5> 34.200
adr<2> data<7> 34.200
adr<3> data<0> 34.200
adr<3> data<1> 34.200
adr<3> data<2> 34.200
adr<3> data<3> 34.200
adr<3> data<4> 34.200
adr<3> data<5> 34.200
adr<3> data<7> 34.200
adr<4> data<0> 34.200
adr<4> data<1> 34.200
adr<4> data<2> 34.200
adr<4> data<3> 34.200
adr<4> data<4> 34.200
adr<4> data<5> 34.200
adr<4> data<7> 34.200
adr<5> data<0> 34.200
adr<5> data<1> 34.200
adr<5> data<2> 34.200
adr<5> data<3> 34.200
adr<5> data<4> 34.200
adr<5> data<5> 34.200
adr<5> data<7> 34.200
adr<6> data<0> 34.200
adr<6> data<1> 34.200
adr<6> data<2> 34.200
adr<6> data<3> 34.200
adr<6> data<4> 34.200
adr<6> data<5> 34.200
adr<6> data<7> 34.200
adr<7> data<0> 34.200
adr<7> data<1> 34.200
adr<7> data<2> 34.200
adr<7> data<3> 34.200
adr<7> data<4> 34.200
adr<7> data<5> 34.200
adr<7> data<7> 34.200
cctl data<0> 34.200
cctl data<1> 34.200
cctl data<2> 34.200
cctl data<3> 34.200
cctl data<4> 34.200
cctl data<5> 34.200
cctl data<7> 34.200
rw data<0> 34.200
rw data<1> 34.200
rw data<2> 34.200
rw data<3> 34.200
rw data<4> 34.200
rw data<5> 34.200
rw data<7> 34.200
rw rom_ce 34.200
s4 ram_rom_adr<14> 34.200
s4 ram_rom_adr<15> 34.200
s4 ram_rom_adr<19> 34.200
s4 ram_rom_adr<22> 34.200
s4 ram_rom_adr<24> 34.200
s4 ram_rom_adr<26> 34.200
adr<0> data<6> 33.200
adr<1> data<6> 33.200
adr<2> data<6> 33.200
adr<3> data<6> 33.200
adr<4> data<6> 33.200
adr<5> data<6> 33.200
adr<6> data<6> 33.200
adr<7> data<6> 33.200
cctl data<6> 33.200
rw data<6> 33.200
s4 ram_rom_adr<16> 33.200
s4 ram_rom_adr<17> 33.200
s4 ram_rom_adr<18> 33.200
s4 ram_rom_adr<20> 33.200
s4 ram_rom_adr<21> 33.200
s4 ram_rom_adr<23> 33.200
s4 ram_rom_adr<25> 33.200
phi2 data<0> 25.200
phi2 data<1> 25.200
phi2 data<2> 25.200
phi2 data<3> 25.200
phi2 data<4> 25.200
phi2 data<5> 25.200
phi2 data<6> 25.200
phi2 data<7> 25.200
adr<12> ram_rom_adr<12> 21.000
adr<12> ram_rom_adr<13> 21.000
eeprom_so data<7> 21.000
s4 ram_rom_adr<13> 21.000
s5 ram_rom_adr<14> 21.000
s5 ram_rom_adr<15> 21.000
s5 ram_rom_adr<19> 21.000
adr<0> ram_rom_adr<0> 20.000
adr<10> ram_rom_adr<10> 20.000
adr<11> ram_rom_adr<11> 20.000
adr<1> ram_rom_adr<1> 20.000
adr<2> ram_rom_adr<2> 20.000
adr<3> ram_rom_adr<3> 20.000
adr<4> ram_rom_adr<4> 20.000
adr<5> ram_rom_adr<5> 20.000
adr<6> ram_rom_adr<6> 20.000
adr<7> ram_rom_adr<7> 20.000
adr<8> ram_rom_adr<8> 20.000
adr<9> ram_rom_adr<9> 20.000
phi2 ram_rom_oe 20.000
phi2short ram_rom_we 20.000
ram_rom_data<0> data<0> 20.000
ram_rom_data<1> data<1> 20.000
ram_rom_data<2> data<2> 20.000
ram_rom_data<3> data<3> 20.000
ram_rom_data<4> data<4> 20.000
ram_rom_data<5> data<5> 20.000
ram_rom_data<6> data<6> 20.000
ram_rom_data<7> data<7> 20.000
rw ram_rom_oe 20.000
rw ram_rom_we 20.000
s5 ram_rom_adr<13> 20.000
s5 ram_rom_adr<16> 20.000
s5 ram_rom_adr<17> 20.000
s5 ram_rom_adr<18> 20.000
data<0> ram_rom_data<0> 16.500
data<1> ram_rom_data<1> 16.500
data<2> ram_rom_data<2> 16.500
data<3> ram_rom_data<3> 16.500
data<4> ram_rom_data<4> 16.500
data<5> ram_rom_data<5> 16.500
data<6> ram_rom_data<6> 16.500
data<7> ram_rom_data<7> 16.500
rw ram_rom_data<0> 11.000
rw ram_rom_data<1> 11.000
rw ram_rom_data<2> 11.000
rw ram_rom_data<3> 11.000
rw ram_rom_data<4> 11.000
rw ram_rom_data<5> 11.000
rw ram_rom_data<6> 11.000
rw ram_rom_data<7> 11.000



Number of paths analyzed: 223
Number of Timing errors: 0
Analysis Completed: Sun Feb 9 23:42:51 2014