Signal Name Total Product Terms Product Terms Location Power Mode Pin Number PinType Pin Use
cfg_bank<14> 16  17_3 17_4 17_5 18_1 18_2 18_3 18_4 18_5 1_1 1_2 1_3 1_4 1_5 2_3 2_4 2_5 MC1 LOW   (b) (b)
ram_rom_data<5> 2  2_1 2_2 MC2 LOW 35 I/O I/O
$OpTx$FX_DC$241 1  3_1 MC3 LOW   (b) (b)
cfg_write_enable2 2  4_1 4_2 MC4 LOW   (b) (b)
ram_rom_data<4> 2  5_1 5_2 MC5 LOW 36 I/O I/O
ram_rom_data<3> 2  6_1 6_2 MC6 LOW 37 I/O I/O
cfg_write_enable 2  7_1 7_2 MC7 LOW   (b) (b)
ram_rom_data<2> 2  8_1 8_2 MC8 LOW 39 I/O I/O
ram_rom_data<1> 2  9_1 9_2 MC9 LOW 40 I/O I/O
cfg_source_ram2 2  10_1 10_2 MC10 LOW   (b) (b)
ram_rom_data<0> 2  11_1 11_2 MC11 LOW 41 I/O I/O
ram_rom_oe 1  12_1 MC12 LOW 42 I/O O
cfg_source_ram 2  13_1 13_2 MC13 LOW   (b) (b)
ram_rom_adr<1> 1  14_1 MC14 LOW 43 I/O O
cfg_bank2<22> 2  15_1 15_2 MC15 LOW 46 I/O (b)
(unused) 0   MC16     (b) (b)
rom_ce 9  15_3 15_4 16_1 16_2 16_3 16_4 16_5 17_1 17_2 MC17 LOW 49 I/O O
(unused) 0   MC18     (b) (b)

Signals Used By Logic in Function Block
  1. $OpTx$FX_DC$149
  2. $OpTx$FX_DC$158
  3. $OpTx$FX_DC$164
  4. $OpTx$FX_DC$185
  5. $OpTx$FX_DC$208
  6. $OpTx$FX_DC$277
  7. $OpTx$INV$144
  8. N91/N91_D2
  9. adr<0>
  10. adr<1>
  11. adr<2>
  12. adr<4>
  13. adr<7>
  14. cctl
  15. cfg_bank2<22>
  16. cfg_bank<14>
  17. cfg_mode<0>
  18. cfg_mode<1>
  19. cfg_mode<2>
  20. cfg_mode<3>
  21. cfg_mode<4>
  22. cfg_mode<5>
  23. cfg_source_ram
  24. cfg_source_ram2
  25. cfg_write_enable
  26. cfg_write_enable2
  27. phi2
  28. data<0>.PIN
  29. data<1>.PIN
  30. data<2>.PIN
  31. data<3>.PIN
  32. data<4>.PIN
  33. data<5>.PIN
  34. reset_n_sync
  35. rw
  36. s4
  37. source_ram_or0000/source_ram_or0000_D2
  38. use_cart_logic/N230/use_cart_logic/N230_D2
  39. use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2
  40. use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2