cpldfit: version M.81d Xilinx Inc. Fitter Report Design Name: TheCart Date: 2- 9-2014, 11:42PM Device Used: XC95144XL-10-TQ100 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 129/144 ( 90%) 512 /720 ( 71%) 378/432 ( 87%) 51 /144 ( 35%) 75 /81 ( 93%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 17/18 53/54 70/90 10/11 FB2 17/18 54/54* 83/90 8/10 FB3 15/18 44/54 74/90 9/10 FB4 15/18 41/54 53/90 10/10* FB5 16/18 40/54 50/90 9/10 FB6 14/18 53/54 81/90 9/10 FB7 18/18* 42/54 40/90 10/10* FB8 17/18 51/54 61/90 10/10* ----- ----- ----- ----- 129/144 378/432 512/720 75/81 * - Resource is exhausted ** Global Control Resources ** Signal 'phi2short' mapped onto global clock net GCK2. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 20 20 | I/O : 68 73 Output : 38 38 | GCK/IO : 3 3 Bidirectional : 16 16 | GTS/IO : 3 4 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 75 75 ** Power Data ** There are 0 macrocells in high performance mode (MCHP). There are 129 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'TheCart.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'cctl' based upon the LOC constraint 'P27'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'phi2' based upon the LOC constraint 'P22'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'phi2_IBUF' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'cctl_IBUF' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. ************************* Summary of Mapped Logic ************************ ** 54 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State data<0> 11 28 FB1_2 11 I/O I/O LOW SLOW data<7> 5 17 FB1_3 12 I/O I/O LOW SLOW data<6> 5 22 FB1_5 13 I/O I/O LOW SLOW eeprom_cs 2 4 FB1_9 16 I/O O LOW SLOW SET eeprom_sck 2 4 FB1_12 18 I/O O LOW SLOW RESET eeprom_si 2 4 FB1_15 20 I/O O LOW SLOW RESET data<4> 8 24 FB2_5 1 GTS/I/O I/O LOW SLOW data<5> 8 24 FB2_11 6 I/O I/O LOW SLOW data<2> 9 25 FB2_14 8 I/O I/O LOW SLOW data<1> 9 26 FB2_15 9 I/O I/O LOW SLOW data<3> 9 25 FB2_17 10 I/O I/O LOW SLOW ram_rom_adr<26> 2 3 FB3_5 24 I/O O LOW SLOW ram_rom_adr<0> 1 1 FB3_6 25 I/O O LOW SLOW ram_rom_adr<17> 4 9 FB3_9 28 I/O O LOW SLOW ram_rom_adr<25> 2 3 FB3_11 29 I/O O LOW SLOW rom_reset 1 1 FB3_12 30 I/O O LOW SLOW RESET ram_rom_data<7> 2 2 FB3_14 32 I/O I/O LOW SLOW ram_rom_data<6> 2 2 FB3_15 33 I/O I/O LOW SLOW ram_rom_data<5> 2 2 FB5_2 35 I/O I/O LOW SLOW ram_rom_data<4> 2 2 FB5_5 36 I/O I/O LOW SLOW ram_rom_data<3> 2 2 FB5_6 37 I/O I/O LOW SLOW ram_rom_data<2> 2 2 FB5_8 39 I/O I/O LOW SLOW ram_rom_data<1> 2 2 FB5_9 40 I/O I/O LOW SLOW ram_rom_data<0> 2 2 FB5_11 41 I/O I/O LOW SLOW ram_rom_oe 1 2 FB5_12 42 I/O O LOW SLOW ram_rom_adr<1> 1 1 FB5_14 43 I/O O LOW SLOW rom_ce 9 11 FB5_17 49 I/O O LOW SLOW ram_rom_adr<15> 4 9 FB6_2 74 I/O O LOW SLOW ram_rom_adr<16> 4 8 FB6_5 76 I/O O LOW SLOW ram_rom_adr<23> 2 3 FB6_6 77 I/O O LOW SLOW ram_rom_adr<24> 2 3 FB6_8 78 I/O O LOW SLOW rd5 9 11 FB6_9 79 I/O O LOW SLOW rd4 5 9 FB6_12 81 I/O O LOW SLOW ram_ce 3 10 FB6_15 85 I/O O LOW SLOW ram_rom_we 1 2 FB7_2 50 I/O O LOW SLOW ram_rom_adr<2> 1 1 FB7_5 52 I/O O LOW SLOW ram_rom_adr<3> 1 1 FB7_6 53 I/O O LOW SLOW ram_rom_adr<4> 1 1 FB7_8 54 I/O O LOW SLOW ram_rom_adr<5> 1 1 FB7_9 55 I/O O LOW SLOW ram_rom_adr<6> 1 1 FB7_11 56 I/O O LOW SLOW Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State ram_rom_adr<7> 1 1 FB7_12 58 I/O O LOW SLOW ram_rom_adr<8> 1 1 FB7_14 59 I/O O LOW SLOW ram_rom_adr<18> 3 8 FB7_15 60 I/O O LOW SLOW ram_rom_adr<19> 3 9 FB7_17 61 I/O O LOW SLOW ram_rom_adr<22> 2 3 FB8_2 63 I/O O LOW SLOW ram_rom_adr<21> 2 3 FB8_5 64 I/O O LOW SLOW ram_rom_adr<20> 2 3 FB8_6 65 I/O O LOW SLOW ram_rom_adr<9> 1 1 FB8_8 66 I/O O LOW SLOW ram_rom_adr<10> 1 1 FB8_9 67 I/O O LOW SLOW ram_rom_adr<11> 1 1 FB8_11 68 I/O O LOW SLOW ram_rom_adr<12> 7 8 FB8_12 70 I/O O LOW SLOW ram_rom_adr<13> 12 13 FB8_14 71 I/O O LOW SLOW ram_rom_adr<14> 3 7 FB8_15 72 I/O O LOW SLOW mod_en 2 12 FB8_17 73 I/O O LOW SLOW RESET ** 75 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State $OpTx$FX_DC$149 1 2 FB1_1 LOW use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 2 5 FB1_4 LOW use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2 2 5 FB1_6 LOW use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2 2 5 FB1_7 LOW use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2 2 5 FB1_8 LOW use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2 2 5 FB1_10 LOW $OpTx$FX_DC$269 2 3 FB1_11 LOW cfg_enable2 5 7 FB1_13 LOW RESET $OpTx$FX_DC$211 5 12 FB1_14 LOW cfg_bank<15> 19 25 FB1_16 LOW RESET $OpTx$FX_DC$208 1 5 FB1_18 LOW use_cart_logic/N230/use_cart_logic/N230_D2 3 7 FB2_1 LOW $OpTx$INV$144 11 12 FB2_2 LOW $OpTx$FX_DC$244 4 6 FB2_3 LOW data_7_IOBUFE/data_7_IOBUFE_TRST 4 18 FB2_4 LOW $OpTx$FX_DC$229 1 7 FB2_6 LOW data_or0000/data_or0000_D2 3 16 FB2_7 LOW $OpTx$FX_DC$221 2 7 FB2_8 LOW N91/N91_D2 2 7 FB2_9 LOW use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 2 12 FB2_10 LOW source_ram_or0000/source_ram_or0000_D2 6 8 FB2_12 LOW $OpTx$FX_DC$207 1 10 FB2_13 LOW $OpTx$FX_DC$185 1 8 FB2_18 LOW cfg_bank2<26> 2 4 FB3_1 LOW RESET cfg_bank<16> 23 24 FB3_3 LOW RESET cfg_bank2<25> 2 4 FB3_7 LOW RESET cfg_bank2<24> 2 4 FB3_8 LOW RESET cfg_bank2<23> 2 4 FB3_10 LOW RESET cfg_bank<20> 11 21 FB3_13 LOW RESET cfg_bank<19> 17 21 FB3_17 LOW RESET $OpTx$FX_DC$158 1 2 FB3_18 LOW cfg_bank<13> 26 23 FB4_1 LOW RESET reset_n_sync 1 1 FB4_4 LOW RESET cfg_mode<5> 2 4 FB4_5 LOW RESET cfg_mode<4> 2 4 FB4_6 LOW RESET cfg_mode<3> 2 4 FB4_7 LOW RESET cfg_mode<2> 2 4 FB4_8 LOW RESET cfg_mode<1> 2 4 FB4_9 LOW RESET cfg_bank2<20> 2 4 FB4_10 LOW RESET cfg_bank2<19> 2 4 FB4_11 LOW RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State cfg_bank2<18> 2 4 FB4_12 LOW RESET cfg_bank2<17> 2 4 FB4_13 LOW RESET cfg_bank2<16> 2 4 FB4_14 LOW RESET cfg_bank2<15> 2 4 FB4_15 LOW RESET cfg_bank2<14> 2 4 FB4_16 LOW RESET cfg_bank2<13> 2 4 FB4_17 LOW RESET cfg_bank<14> 16 25 FB5_1 LOW RESET $OpTx$FX_DC$241 1 2 FB5_3 LOW cfg_write_enable2 2 4 FB5_4 LOW RESET cfg_write_enable 2 4 FB5_7 LOW RESET cfg_source_ram2 2 4 FB5_10 LOW RESET cfg_source_ram 2 4 FB5_13 LOW RESET cfg_bank2<22> 2 4 FB5_15 LOW RESET $OpTx$FX_DC$209 1 2 FB6_3 LOW $OpTx$FX_DC$164 1 2 FB6_4 LOW use_cart_logic/oss_bank<1> 2 11 FB6_7 LOW RESET $OpTx$FX_DC$277 4 7 FB6_10 LOW cfg_mode<0> 2 4 FB6_11 LOW SET use_cart_logic/N117/use_cart_logic/N117_D2 14 15 FB6_14 LOW cfg_enable 28 26 FB6_18 LOW SET reset_n_sync1 1 1 FB7_1 LOW RESET $OpTx$FX_DC$217 1 2 FB7_3 LOW sic_axxx_enable 2 4 FB7_4 LOW SET sic_8xxx_enable 2 4 FB7_7 LOW RESET cfg_bank<26> 2 4 FB7_10 LOW RESET cfg_bank<25> 2 4 FB7_13 LOW RESET cfg_bank2<21> 2 4 FB7_16 LOW RESET cfg_bank<18> 14 24 FB7_18 LOW RESET cfg_bank<17> 17 23 FB8_1 LOW RESET $OpTx$FX_DC$173 1 6 FB8_3 LOW use_cart_logic/oss_bank<0> 2 11 FB8_4 LOW RESET cfg_bank<24> 2 4 FB8_7 LOW RESET cfg_bank<23> 2 4 FB8_10 LOW RESET cfg_bank<22> 2 4 FB8_13 LOW RESET cfg_bank<21> 2 4 FB8_16 LOW RESET ** 21 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use adr<11> FB1_6 14 I/O I adr<10> FB1_8 15 I/O I eeprom_so FB1_11 17 I/O I phi2 FB1_17 22 GCK/I/O I rw FB2_2 99 GSR/I/O I s4 FB2_8 3 GTS/I/O I s5 FB2_9 4 GTS/I/O I phi2short FB3_2 23 GCK/I/O GCK/I cctl FB3_8 27 GCK/I/O I adr<4> FB4_2 87 I/O I adr<2> FB4_5 89 I/O I adr<5> FB4_6 90 I/O I adr<1> FB4_8 91 I/O I adr<6> FB4_9 92 I/O I adr<0> FB4_11 93 I/O I adr<7> FB4_12 94 I/O I adr<8> FB4_14 95 I/O I adr<9> FB4_15 96 I/O I adr<12> FB4_17 97 I/O I reset_n FB6_14 82 I/O I adr<3> FB6_17 86 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 53/1 Number of signals used by logic mapping into function block: 53 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use $OpTx$FX_DC$149 1 0 \/4 0 FB1_1 (b) (b) data<0> 11 6<- 0 0 FB1_2 11 I/O I/O data<7> 5 2<- /\2 0 FB1_3 12 I/O I/O use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 2 0 /\2 1 FB1_4 (b) (b) data<6> 5 0 0 0 FB1_5 13 I/O I/O use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2 2 0 0 3 FB1_6 14 I/O I use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2 2 0 0 3 FB1_7 (b) (b) use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2 2 0 0 3 FB1_8 15 I/O I eeprom_cs 2 0 0 3 FB1_9 16 I/O O use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2 2 0 0 3 FB1_10 (b) (b) $OpTx$FX_DC$269 2 0 0 3 FB1_11 17 I/O I eeprom_sck 2 0 \/2 1 FB1_12 18 I/O O cfg_enable2 5 2<- \/2 0 FB1_13 (b) (b) $OpTx$FX_DC$211 5 2<- \/2 0 FB1_14 19 I/O (b) eeprom_si 2 2<- \/5 0 FB1_15 20 I/O O cfg_bank<15> 19 14<- 0 0 FB1_16 (b) (b) (unused) 0 0 /\5 0 FB1_17 22 GCK/I/O I $OpTx$FX_DC$208 1 0 /\4 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$149 19: cfg_bank2<13> 37: cfg_write_enable 2: $OpTx$FX_DC$158 20: cfg_bank2<19> 38: data_7_IOBUFE/data_7_IOBUFE_TRST 3: $OpTx$FX_DC$185 21: cfg_bank2<20> 39: data_or0000/data_or0000_D2 4: $OpTx$FX_DC$208 22: cfg_bank2<21> 40: eeprom_cs 5: $OpTx$INV$144 23: cfg_bank<13> 41: eeprom_sck 6: ram_rom_data<7>.PIN 24: cfg_bank<14> 42: eeprom_si 7: ram_rom_data<6>.PIN 25: cfg_bank<15> 43: eeprom_so 8: ram_rom_data<0>.PIN 26: cfg_bank<19> 44: mod_en 9: N91/N91_D2 27: cfg_bank<20> 45: data<0>.PIN 10: adr<0> 28: cfg_bank<21> 46: data<1>.PIN 11: adr<1> 29: cfg_enable 47: data<2>.PIN 12: adr<2> 30: cfg_enable2 48: data<7>.PIN 13: adr<3> 31: cfg_mode<0> 49: reset_n_sync 14: adr<4> 32: cfg_mode<1> 50: rw 15: adr<5> 33: cfg_mode<2> 51: sic_axxx_enable 16: adr<6> 34: cfg_mode<3> 52: use_cart_logic/N230/use_cart_logic/N230_D2 17: adr<7> 35: cfg_mode<4> 53: use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 18: cctl 36: cfg_mode<5> Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs $OpTx$FX_DC$149 ..............................XX............................ 2 data<0> X......X.XXXXXXXXXX..XXX...XXXX.XXXXXXX....X.....X.......... 28 data<7> .....X...XXXXXXXXX..X.....X..........XX...XX.....X.......... 17 use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 ..X......XXX....................................X........... 5 data<6> X.....X..XXXXXXXXX.X.....X......XXXX.XX....X.....XX......... 22 use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2 ..X......XXX....................................X........... 5 use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2 ..X......XXX....................................X........... 5 use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2 ..X......XXX....................................X........... 5 eeprom_cs .......................................X.....X..X...X....... 4 use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2 ..X......XXX....................................X........... 5 $OpTx$FX_DC$269 .X...........X.....................X........................ 3 eeprom_sck ........................................X...X...X...X....... 4 cfg_enable2 ..X......XXX.................X..............X...X........... 7 $OpTx$FX_DC$211 .X.X....X.......XX............XXXXXX............X........... 12 eeprom_si .........................................X.....XX...X....... 4 cfg_bank<15> ...XX...XXXXXXXXXX......X.....XXXXXX.......X.XX.XX.X........ 25 $OpTx$FX_DC$208 .............XXXX..........................X................ 5 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 54/0 Number of signals used by logic mapping into function block: 54 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use use_cart_logic/N230/use_cart_logic/N230_D2 3 0 \/2 0 FB2_1 (b) (b) $OpTx$INV$144 11 6<- 0 0 FB2_2 99 GSR/I/O I $OpTx$FX_DC$244 4 3<- /\4 0 FB2_3 (b) (b) data_7_IOBUFE/data_7_IOBUFE_TRST 4 2<- /\3 0 FB2_4 (b) (b) data<4> 8 5<- /\2 0 FB2_5 1 GTS/I/O I/O $OpTx$FX_DC$229 1 1<- /\5 0 FB2_6 2 GTS/I/O (b) data_or0000/data_or0000_D2 3 0 /\1 1 FB2_7 (b) (b) $OpTx$FX_DC$221 2 0 0 3 FB2_8 3 GTS/I/O I N91/N91_D2 2 0 \/1 2 FB2_9 4 GTS/I/O I use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 2 1<- \/4 0 FB2_10 (b) (b) data<5> 8 4<- \/1 0 FB2_11 6 I/O I/O source_ram_or0000/source_ram_or0000_D2 6 1<- 0 0 FB2_12 7 I/O (b) $OpTx$FX_DC$207 1 0 \/4 0 FB2_13 (b) (b) data<2> 9 4<- 0 0 FB2_14 8 I/O I/O data<1> 9 4<- 0 0 FB2_15 9 I/O I/O (unused) 0 0 /\4 1 FB2_16 (b) (b) data<3> 9 4<- 0 0 FB2_17 10 I/O I/O $OpTx$FX_DC$185 1 0 /\4 0 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$149 19: cfg_bank2<15> 37: cfg_bank<26> 2: $OpTx$FX_DC$164 20: cfg_bank2<16> 38: cfg_mode<0> 3: $OpTx$FX_DC$208 21: cfg_bank2<17> 39: cfg_mode<1> 4: ram_rom_data<5>.PIN 22: cfg_bank2<18> 40: cfg_mode<2> 5: ram_rom_data<4>.PIN 23: cfg_bank2<22> 41: cfg_mode<3> 6: ram_rom_data<3>.PIN 24: cfg_bank2<23> 42: cfg_mode<4> 7: ram_rom_data<2>.PIN 25: cfg_bank2<24> 43: cfg_mode<5> 8: ram_rom_data<1>.PIN 26: cfg_bank2<25> 44: cfg_source_ram 9: adr<0> 27: cfg_bank2<26> 45: cfg_source_ram2 10: adr<1> 28: cfg_bank<14> 46: cfg_write_enable2 11: adr<2> 29: cfg_bank<15> 47: data_7_IOBUFE/data_7_IOBUFE_TRST 12: adr<3> 30: cfg_bank<16> 48: data_or0000/data_or0000_D2 13: adr<4> 31: cfg_bank<17> 49: mod_en 14: adr<5> 32: cfg_bank<18> 50: phi2 15: adr<6> 33: cfg_bank<22> 51: reset_n_sync 16: adr<7> 34: cfg_bank<23> 52: rw 17: cctl 35: cfg_bank<24> 53: sic_8xxx_enable 18: cfg_bank2<14> 36: cfg_bank<25> 54: use_cart_logic/N117/use_cart_logic/N117_D2 Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs use_cart_logic/N230/use_cart_logic/N230_D2 ............XXXX.....................XXX.................... 7 $OpTx$INV$144 .X..........XXXX.....................XXXXXX........X........ 12 $OpTx$FX_DC$244 ............X.XX.....................X.XX................... 6 data_7_IOBUFE/data_7_IOBUFE_TRST X.......XXXXXXXXX......................XXXX.....XX.X.X...... 18 data<4> X...X...XXXXXXXXX...X....X....XX...X...XXXX...XXX..X........ 24 $OpTx$FX_DC$229 X.X.............X......................XXXX................. 7 data_or0000/data_or0000_D2 X.......XXXXXXXXX......................XXXX.....X..X........ 16 $OpTx$FX_DC$221 ..X.....XXXX....X..................................X........ 7 N91/N91_D2 ..X.....XXXX....X..................................X........ 7 use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 ........XXXXXXXXX...............................X.XX........ 12 data<5> X..X....XXXXXXXXX....X....X....X....X..XXXX...XXX..XX....... 24 source_ram_or0000/source_ram_or0000_D2 XX...................................XXXXXX................. 8 $OpTx$FX_DC$207 X............XXXX......................XXXX........X........ 10 data<2> X.....X.XXXXXXXXX.X....X....XX...X.....XXXX..XXXX..X........ 25 data<1> X......XXXXXXXXXXX....X....XX...X.....XXXXXX..XXX..X........ 26 data<3> X....X..XXXXXXXXX..X....X....XX...X....XXXX.X.XXX..X........ 25 $OpTx$FX_DC$185 ...........XXXXXX...............................X..X........ 8 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 44/10 Number of signals used by logic mapping into function block: 44 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use cfg_bank2<26> 2 0 \/3 0 FB3_1 (b) (b) (unused) 0 0 \/5 0 FB3_2 23 GCK/I/O GCK/I cfg_bank<16> 23 18<- 0 0 FB3_3 (b) (b) (unused) 0 0 /\5 0 FB3_4 (b) (b) ram_rom_adr<26> 2 2<- /\5 0 FB3_5 24 I/O O ram_rom_adr<0> 1 0 /\2 2 FB3_6 25 I/O O cfg_bank2<25> 2 0 0 3 FB3_7 (b) (b) cfg_bank2<24> 2 0 0 3 FB3_8 27 GCK/I/O I ram_rom_adr<17> 4 0 0 1 FB3_9 28 I/O O cfg_bank2<23> 2 0 0 3 FB3_10 (b) (b) ram_rom_adr<25> 2 0 0 3 FB3_11 29 I/O O rom_reset 1 0 \/4 0 FB3_12 30 I/O O cfg_bank<20> 11 6<- 0 0 FB3_13 (b) (b) ram_rom_data<7> 2 0 /\2 1 FB3_14 32 I/O I/O ram_rom_data<6> 2 0 \/3 0 FB3_15 33 I/O I/O (unused) 0 0 \/5 0 FB3_16 (b) (b) cfg_bank<19> 17 12<- 0 0 FB3_17 34 I/O (b) $OpTx$FX_DC$158 1 0 /\4 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$158 16: cctl 31: cfg_mode<3> 2: $OpTx$FX_DC$173 17: cfg_bank2<17> 32: cfg_mode<4> 3: $OpTx$FX_DC$185 18: cfg_bank2<23> 33: cfg_mode<5> 4: $OpTx$FX_DC$208 19: cfg_bank2<24> 34: mod_en 5: $OpTx$FX_DC$211 20: cfg_bank2<25> 35: data<2>.PIN 6: $OpTx$FX_DC$217 21: cfg_bank2<26> 36: data<3>.PIN 7: $OpTx$FX_DC$221 22: cfg_bank<16> 37: data<4>.PIN 8: adr<0> 23: cfg_bank<17> 38: data<5>.PIN 9: adr<1> 24: cfg_bank<19> 39: data<6>.PIN 10: adr<2> 25: cfg_bank<20> 40: data<7>.PIN 11: adr<3> 26: cfg_bank<25> 41: reset_n_sync 12: adr<4> 27: cfg_bank<26> 42: rw 13: adr<5> 28: cfg_mode<0> 43: s5 14: adr<6> 29: cfg_mode<1> 44: use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2 15: adr<7> 30: cfg_mode<2> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs cfg_bank2<26> ....................X................X..X..X...... 4 cfg_bank<16> X..XX..XXXXXXXXX.....X.....XXXXXXXXX....XX........ 24 ram_rom_adr<26> .X..................X.....X....................... 3 ram_rom_adr<0> .......X.......................................... 1 cfg_bank2<25> ...................X................X...X..X...... 4 cfg_bank2<24> ..................X................X....X..X...... 4 ram_rom_adr<17> .X..............X.....X....XXX.XX.........X....... 9 cfg_bank2<23> .................X................X.....X..X...... 4 ram_rom_adr<25> .X.................X.....X........................ 3 rom_reset ........................................X......... 1 cfg_bank<20> ..XX.XXXXX...XXX........X..XXXXXX.....XXXX........ 21 ram_rom_data<7> .......................................X.X........ 2 ram_rom_data<6> ......................................X..X........ 2 cfg_bank<19> ..XX..XXXX..XXXX.......X...XXXXXX....XX.XX........ 21 $OpTx$FX_DC$158 ............XX.................................... 2 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 41/13 Number of signals used by logic mapping into function block: 41 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use cfg_bank<13> 26 21<- 0 0 FB4_1 (b) (b) (unused) 0 0 /\5 0 FB4_2 87 I/O I (unused) 0 0 /\5 0 FB4_3 (b) (b) reset_n_sync 1 0 /\2 2 FB4_4 (b) (b) cfg_mode<5> 2 0 0 3 FB4_5 89 I/O I cfg_mode<4> 2 0 0 3 FB4_6 90 I/O I cfg_mode<3> 2 0 0 3 FB4_7 (b) (b) cfg_mode<2> 2 0 0 3 FB4_8 91 I/O I cfg_mode<1> 2 0 0 3 FB4_9 92 I/O I cfg_bank2<20> 2 0 0 3 FB4_10 (b) (b) cfg_bank2<19> 2 0 0 3 FB4_11 93 I/O I cfg_bank2<18> 2 0 0 3 FB4_12 94 I/O I cfg_bank2<17> 2 0 0 3 FB4_13 (b) (b) cfg_bank2<16> 2 0 0 3 FB4_14 95 I/O I cfg_bank2<15> 2 0 0 3 FB4_15 96 I/O I cfg_bank2<14> 2 0 \/1 2 FB4_16 (b) (b) cfg_bank2<13> 2 1<- \/4 0 FB4_17 97 I/O I (unused) 0 0 \/5 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$158 15: cfg_bank2<15> 29: data<1>.PIN 2: $OpTx$FX_DC$185 16: cfg_bank2<16> 30: data<2>.PIN 3: $OpTx$FX_DC$208 17: cfg_bank2<17> 31: data<3>.PIN 4: $OpTx$FX_DC$244 18: cfg_bank2<18> 32: data<4>.PIN 5: N91/N91_D2 19: cfg_bank2<19> 33: data<5>.PIN 6: adr<0> 20: cfg_bank2<20> 34: data<6>.PIN 7: adr<1> 21: cfg_bank<13> 35: data<7>.PIN 8: adr<2> 22: cfg_mode<0> 36: reset_n_sync 9: adr<4> 23: cfg_mode<1> 37: reset_n_sync1 10: adr<5> 24: cfg_mode<2> 38: rw 11: adr<7> 25: cfg_mode<3> 39: use_cart_logic/N230/use_cart_logic/N230_D2 12: cctl 26: cfg_mode<4> 40: use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2 13: cfg_bank2<13> 27: cfg_mode<5> 41: use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2 14: cfg_bank2<14> 28: data<0>.PIN Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs cfg_bank<13> XXXXXXXXXXXX........XXXXXXXX.......X.XX........... 23 reset_n_sync ....................................X............. 1 cfg_mode<5> ..........................X.....X..X....X......... 4 cfg_mode<4> .........................X.....X...X....X......... 4 cfg_mode<3> ........................X.....X....X....X......... 4 cfg_mode<2> .......................X.....X.....X....X......... 4 cfg_mode<1> ......................X.....X......X....X......... 4 cfg_bank2<20> ...................X..............XX...X.......... 4 cfg_bank2<19> ..................X..............X.X...X.......... 4 cfg_bank2<18> .................X..............X..X...X.......... 4 cfg_bank2<17> ................X..............X...X...X.......... 4 cfg_bank2<16> ...............X..............X....X...X.......... 4 cfg_bank2<15> ..............X..............X.....X...X.......... 4 cfg_bank2<14> .............X..............X......X...X.......... 4 cfg_bank2<13> ............X..............X.......X...X.......... 4 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 40/14 Number of signals used by logic mapping into function block: 40 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use cfg_bank<14> 16 11<- 0 0 FB5_1 (b) (b) ram_rom_data<5> 2 0 /\3 0 FB5_2 35 I/O I/O $OpTx$FX_DC$241 1 0 0 4 FB5_3 (b) (b) cfg_write_enable2 2 0 0 3 FB5_4 (b) (b) ram_rom_data<4> 2 0 0 3 FB5_5 36 I/O I/O ram_rom_data<3> 2 0 0 3 FB5_6 37 I/O I/O cfg_write_enable 2 0 0 3 FB5_7 (b) (b) ram_rom_data<2> 2 0 0 3 FB5_8 39 I/O I/O ram_rom_data<1> 2 0 0 3 FB5_9 40 I/O I/O cfg_source_ram2 2 0 0 3 FB5_10 (b) (b) ram_rom_data<0> 2 0 0 3 FB5_11 41 I/O I/O ram_rom_oe 1 0 0 4 FB5_12 42 I/O O cfg_source_ram 2 0 0 3 FB5_13 (b) (b) ram_rom_adr<1> 1 0 0 4 FB5_14 43 I/O O cfg_bank2<22> 2 0 \/2 1 FB5_15 46 I/O (b) (unused) 0 0 \/5 0 FB5_16 (b) (b) rom_ce 9 7<- \/3 0 FB5_17 49 I/O O (unused) 0 0 \/5 0 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$149 15: cfg_bank2<22> 28: data<0>.PIN 2: $OpTx$FX_DC$158 16: cfg_bank<14> 29: data<1>.PIN 3: $OpTx$FX_DC$164 17: cfg_mode<0> 30: data<2>.PIN 4: $OpTx$FX_DC$185 18: cfg_mode<1> 31: data<3>.PIN 5: $OpTx$FX_DC$208 19: cfg_mode<2> 32: data<4>.PIN 6: $OpTx$FX_DC$277 20: cfg_mode<3> 33: data<5>.PIN 7: $OpTx$INV$144 21: cfg_mode<4> 34: reset_n_sync 8: N91/N91_D2 22: cfg_mode<5> 35: rw 9: adr<0> 23: cfg_source_ram 36: s4 10: adr<1> 24: cfg_source_ram2 37: source_ram_or0000/source_ram_or0000_D2 11: adr<2> 25: cfg_write_enable 38: use_cart_logic/N230/use_cart_logic/N230_D2 12: adr<4> 26: cfg_write_enable2 39: use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2 13: adr<7> 27: phi2 40: use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 14: cctl Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs cfg_bank<14> XXXXX.XXXXXXXX.XXXXXXX.....XX....XX..X............ 25 ram_rom_data<5> ................................X.X............... 2 $OpTx$FX_DC$241 ........X.X....................................... 2 cfg_write_enable2 .........................X...X...X.....X.......... 4 ram_rom_data<4> ...............................X..X............... 2 ram_rom_data<3> ..............................X...X............... 2 cfg_write_enable ........................X..X.....X.....X.......... 4 ram_rom_data<2> .............................X....X............... 2 ram_rom_data<1> ............................X.....X............... 2 cfg_source_ram2 .......................X......X..X.....X.......... 4 ram_rom_data<0> ...........................X......X............... 2 ram_rom_oe ..........................X.......X............... 2 cfg_source_ram ......................X.....X....X.....X.......... 4 ram_rom_adr<1> .........X........................................ 1 cfg_bank2<22> ..............X.............X....X....X........... 4 rom_ce X....X............XXXXXX..........XXX............. 11 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 53/1 Number of signals used by logic mapping into function block: 53 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\5 0 FB6_1 (b) (b) ram_rom_adr<15> 4 4<- /\5 0 FB6_2 74 I/O O $OpTx$FX_DC$209 1 0 /\4 0 FB6_3 (b) (b) $OpTx$FX_DC$164 1 0 0 4 FB6_4 (b) (b) ram_rom_adr<16> 4 0 0 1 FB6_5 76 I/O O ram_rom_adr<23> 2 0 0 3 FB6_6 77 I/O O use_cart_logic/oss_bank<1> 2 0 \/2 1 FB6_7 (b) (b) ram_rom_adr<24> 2 2<- \/5 0 FB6_8 78 I/O O rd5 9 5<- \/1 0 FB6_9 79 I/O O $OpTx$FX_DC$277 4 1<- \/2 0 FB6_10 (b) (b) cfg_mode<0> 2 2<- \/5 0 FB6_11 80 I/O (b) rd4 5 5<- \/5 0 FB6_12 81 I/O O (unused) 0 0 \/5 0 FB6_13 (b) (b) use_cart_logic/N117/use_cart_logic/N117_D2 14 10<- \/1 0 FB6_14 82 I/O I ram_ce 3 1<- \/3 0 FB6_15 85 I/O O (unused) 0 0 \/5 0 FB6_16 (b) (b) (unused) 0 0 \/5 0 FB6_17 86 I/O I cfg_enable 28 23<- 0 0 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$149 19: cctl 37: cfg_source_ram2 2: $OpTx$FX_DC$158 20: cfg_bank2<15> 38: cfg_write_enable 3: $OpTx$FX_DC$173 21: cfg_bank2<16> 39: cfg_write_enable2 4: $OpTx$FX_DC$185 22: cfg_bank2<23> 40: data<0>.PIN 5: $OpTx$FX_DC$208 23: cfg_bank2<24> 41: data<7>.PIN 6: $OpTx$FX_DC$209 24: cfg_bank<15> 42: reset_n_sync 7: $OpTx$FX_DC$229 25: cfg_bank<16> 43: rw 8: $OpTx$FX_DC$241 26: cfg_bank<23> 44: s4 9: $OpTx$FX_DC$244 27: cfg_bank<24> 45: s5 10: $OpTx$FX_DC$269 28: cfg_enable 46: sic_8xxx_enable 11: $OpTx$FX_DC$277 29: cfg_enable2 47: sic_axxx_enable 12: adr<0> 30: cfg_mode<0> 48: source_ram_or0000/source_ram_or0000_D2 13: adr<1> 31: cfg_mode<1> 49: use_cart_logic/N117/use_cart_logic/N117_D2 14: adr<2> 32: cfg_mode<2> 50: use_cart_logic/N230/use_cart_logic/N230_D2 15: adr<3> 33: cfg_mode<3> 51: use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2 16: adr<4> 34: cfg_mode<4> 52: use_cart_logic/oss_bank<0> 17: adr<5> 35: cfg_mode<5> 53: use_cart_logic/oss_bank<1> 18: adr<7> 36: cfg_source_ram Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs ram_rom_adr<15> X.X................X...X......XX.XX.........X............... 9 $OpTx$FX_DC$209 .............................X..X........................... 2 $OpTx$FX_DC$164 ..............................XX............................ 2 ram_rom_adr<16> ..X.................X...X.....XX.XX.........X............... 8 ram_rom_adr<23> ..X..................X...X.................................. 3 use_cart_logic/oss_bank<1> X...X.X....X......X............XXXX......X..........X....... 11 ram_rom_adr<24> ..X...................X...X................................. 3 rd5 X..........................X.XXXXXX...........X....XX....... 11 $OpTx$FX_DC$277 ..X..................................XX...XX...XX........... 7 cfg_mode<0> .............................X.........X.X........X......... 4 rd4 X..........................XX.XXXXX..........X.............. 9 use_cart_logic/N117/use_cart_logic/N117_D2 X..........................XXXXXXXX........XXXX....XX....... 15 ram_ce X.........X....................XXXXXX......X...X............ 10 cfg_enable .X.XXX.XXX..XXXXXXX........X.XXXXXX....XXXX......X.......... 26 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 42/12 Number of signals used by logic mapping into function block: 42 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use reset_n_sync1 1 0 /\4 0 FB7_1 (b) (b) ram_rom_we 1 0 0 4 FB7_2 50 I/O O $OpTx$FX_DC$217 1 0 0 4 FB7_3 (b) (b) sic_axxx_enable 2 0 0 3 FB7_4 (b) (b) ram_rom_adr<2> 1 0 0 4 FB7_5 52 I/O O ram_rom_adr<3> 1 0 0 4 FB7_6 53 I/O O sic_8xxx_enable 2 0 0 3 FB7_7 (b) (b) ram_rom_adr<4> 1 0 0 4 FB7_8 54 I/O O ram_rom_adr<5> 1 0 0 4 FB7_9 55 I/O O cfg_bank<26> 2 0 0 3 FB7_10 (b) (b) ram_rom_adr<6> 1 0 0 4 FB7_11 56 I/O O ram_rom_adr<7> 1 0 0 4 FB7_12 58 I/O O cfg_bank<25> 2 0 0 3 FB7_13 (b) (b) ram_rom_adr<8> 1 0 0 4 FB7_14 59 I/O O ram_rom_adr<18> 3 0 0 2 FB7_15 60 I/O O cfg_bank2<21> 2 0 \/3 0 FB7_16 (b) (b) ram_rom_adr<19> 3 3<- \/5 0 FB7_17 61 I/O O cfg_bank<18> 14 9<- 0 0 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$149 15: cctl 29: mod_en 2: $OpTx$FX_DC$173 16: cfg_bank2<18> 30: phi2short 3: $OpTx$FX_DC$207 17: cfg_bank2<19> 31: data<0>.PIN 4: $OpTx$FX_DC$208 18: cfg_bank2<21> 32: data<4>.PIN 5: $OpTx$FX_DC$211 19: cfg_bank<18> 33: data<5>.PIN 6: adr<0> 20: cfg_bank<19> 34: data<6>.PIN 7: adr<1> 21: cfg_bank<25> 35: reset_n 8: adr<2> 22: cfg_bank<26> 36: reset_n_sync 9: adr<3> 23: cfg_mode<0> 37: rw 10: adr<4> 24: cfg_mode<1> 38: s5 11: adr<5> 25: cfg_mode<2> 39: sic_8xxx_enable 12: adr<6> 26: cfg_mode<3> 40: sic_axxx_enable 13: adr<7> 27: cfg_mode<4> 41: use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2 14: adr<8> 28: cfg_mode<5> 42: use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2 Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs reset_n_sync1 ..................................X............... 1 ram_rom_we .............................X......X............. 2 $OpTx$FX_DC$217 .......................X..X....................... 2 sic_axxx_enable ..X..............................X.X...X.......... 4 ram_rom_adr<2> .......X.......................................... 1 ram_rom_adr<3> ........X......................................... 1 sic_8xxx_enable ..X.............................X..X..X........... 4 ram_rom_adr<4> .........X........................................ 1 ram_rom_adr<5> ..........X....................................... 1 cfg_bank<26> .....................X..........X..X.....X........ 4 ram_rom_adr<6> ...........X...................................... 1 ram_rom_adr<7> ............X..................................... 1 cfg_bank<25> ....................X..........X...X.....X........ 4 ram_rom_adr<8> .............X.................................... 1 ram_rom_adr<18> .X.............X..X....XX.XX.........X............ 8 cfg_bank2<21> .................X............X....X....X......... 4 ram_rom_adr<19> .X..............X..X..XXX.XX.........X............ 9 cfg_bank<18> X..XXXXXXXXXX.X...X...XXXXXXX..XX..XX............. 24 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 51/3 Number of signals used by logic mapping into function block: 51 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use cfg_bank<17> 17 12<- 0 0 FB8_1 (b) (b) ram_rom_adr<22> 2 1<- /\4 0 FB8_2 63 I/O O $OpTx$FX_DC$173 1 0 /\1 3 FB8_3 (b) (b) use_cart_logic/oss_bank<0> 2 0 0 3 FB8_4 (b) (b) ram_rom_adr<21> 2 0 0 3 FB8_5 64 I/O O ram_rom_adr<20> 2 0 0 3 FB8_6 65 I/O O cfg_bank<24> 2 0 0 3 FB8_7 (b) (b) ram_rom_adr<9> 1 0 0 4 FB8_8 66 I/O O ram_rom_adr<10> 1 0 0 4 FB8_9 67 I/O O cfg_bank<23> 2 0 0 3 FB8_10 (b) (b) ram_rom_adr<11> 1 0 \/2 2 FB8_11 68 I/O O ram_rom_adr<12> 7 2<- 0 0 FB8_12 70 I/O O cfg_bank<22> 2 0 \/3 0 FB8_13 (b) (b) ram_rom_adr<13> 12 7<- 0 0 FB8_14 71 I/O O ram_rom_adr<14> 3 2<- /\4 0 FB8_15 72 I/O O cfg_bank<21> 2 0 /\2 1 FB8_16 (b) (b) mod_en 2 0 \/3 0 FB8_17 73 I/O O (unused) 0 0 \/5 0 FB8_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$149 18: adr<9> 35: cfg_mode<2> 2: $OpTx$FX_DC$164 19: cctl 36: cfg_mode<3> 3: $OpTx$FX_DC$173 20: cfg_bank2<13> 37: cfg_mode<4> 4: $OpTx$FX_DC$208 21: cfg_bank2<14> 38: cfg_mode<5> 5: $OpTx$FX_DC$211 22: cfg_bank2<20> 39: mod_en 6: $OpTx$FX_DC$229 23: cfg_bank2<21> 40: data<0>.PIN 7: adr<0> 24: cfg_bank2<22> 41: data<1>.PIN 8: adr<10> 25: cfg_bank<13> 42: data<2>.PIN 9: adr<11> 26: cfg_bank<14> 43: data<3>.PIN 10: adr<12> 27: cfg_bank<17> 44: data<4>.PIN 11: adr<1> 28: cfg_bank<20> 45: reset_n_sync 12: adr<2> 29: cfg_bank<21> 46: rw 13: adr<3> 30: cfg_bank<22> 47: s4 14: adr<4> 31: cfg_bank<23> 48: s5 15: adr<5> 32: cfg_bank<24> 49: use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2 16: adr<6> 33: cfg_mode<0> 50: use_cart_logic/oss_bank<0> 17: adr<7> 34: cfg_mode<1> 51: use_cart_logic/oss_bank<1> Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs cfg_bank<17> ...XX.X...XXXXXXX.X.......X.....XXXXXXX...XXXX.............. 23 ram_rom_adr<22> ..X....................X.....X.............................. 3 $OpTx$FX_DC$173 X.................................XXXX........X............. 6 use_cart_logic/oss_bank<0> X..X.X......X.....X...............XXXX......X....X.......... 11 ram_rom_adr<21> ..X...................X.....X............................... 3 ram_rom_adr<20> ..X..................X.....X................................ 3 cfg_bank<24> ...............................X..........X.X...X........... 4 ram_rom_adr<9> .................X.......................................... 1 ram_rom_adr<10> .......X.................................................... 1 cfg_bank<23> ..............................X..........X..X...X........... 4 ram_rom_adr<11> ........X................................................... 1 ram_rom_adr<12> X........X........................XXXX...........XX......... 8 cfg_bank<22> .............................X..........X...X...X........... 4 ram_rom_adr<13> XX.......X.........X....X.........XXXX........XX.XX......... 13 ram_rom_adr<14> .XX.................X....X..........XX.........X............ 7 cfg_bank<21> ............................X..........X....X...X........... 4 mod_en ......X...XXXXXXX.X...................X.....XX.............. 12 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$FX_DC$149 <= (NOT cfg_mode(1) AND NOT cfg_mode(0)); $OpTx$FX_DC$158 <= (NOT adr(6) AND NOT adr(5)); $OpTx$FX_DC$164 <= (cfg_mode(2) AND cfg_mode(1)); $OpTx$FX_DC$173 <= (NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT s4 AND $OpTx$FX_DC$149); $OpTx$FX_DC$185 <= (NOT rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT mod_en AND adr(7) AND adr(5) AND NOT adr(4)); $OpTx$FX_DC$207 <= (NOT rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND $OpTx$FX_DC$149); $OpTx$FX_DC$208 <= (NOT adr(6) AND NOT mod_en AND adr(7) AND adr(5) AND NOT adr(4)); $OpTx$FX_DC$209 <= (NOT cfg_mode(0) AND NOT cfg_mode(3)); $OpTx$FX_DC$211 <= ((NOT cctl AND cfg_mode(2) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND reset_n_sync AND NOT $OpTx$FX_DC$208 AND NOT $OpTx$FX_DC$158) OR (NOT cctl AND cfg_mode(5) AND cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (reset_n_sync AND NOT N91/N91_D2) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND adr(7) AND reset_n_sync AND NOT $OpTx$FX_DC$208)); $OpTx$FX_DC$217 <= (cfg_mode(1) AND NOT cfg_mode(4)); $OpTx$FX_DC$221 <= ((NOT cctl AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT adr(1))); $OpTx$FX_DC$229 <= (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208); $OpTx$FX_DC$241 <= (NOT adr(2) AND NOT adr(0)); $OpTx$FX_DC$244 <= ((NOT adr(6) AND NOT cfg_mode(2) AND cfg_mode(3)) OR (cfg_mode(2) AND cfg_mode(0) AND adr(7)) OR (cfg_mode(2) AND cfg_mode(0) AND adr(4)) OR (adr(6) AND cfg_mode(2) AND cfg_mode(0))); $OpTx$FX_DC$269 <= ((NOT cfg_mode(5) AND adr(4)) OR (NOT cfg_mode(5) AND NOT $OpTx$FX_DC$158)); $OpTx$FX_DC$277 <= ((NOT use_cart_logic/N117/use_cart_logic/N117_D2) OR (NOT rw AND NOT cfg_write_enable2 AND NOT s4 AND NOT source_ram_or0000/source_ram_or0000_D2) OR (NOT rw AND NOT cfg_write_enable2 AND NOT cfg_write_enable) OR (NOT rw AND NOT cfg_write_enable AND NOT $OpTx$FX_DC$173)); $OpTx$INV$144 <= ((NOT rw AND NOT adr(6) AND cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND NOT adr(7) AND NOT adr(5)) OR (adr(6) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND adr(5)) OR (NOT adr(6) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND NOT adr(4)) OR (adr(6) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND NOT adr(5) AND adr(4)) OR (adr(6) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND NOT adr(7) AND adr(5) AND adr(4)) OR (NOT adr(6) AND cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND NOT adr(4)) OR (NOT rw AND cfg_mode(5) AND cfg_mode(4) AND NOT $OpTx$FX_DC$164) OR (NOT rw AND cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3)) OR (NOT rw AND cfg_mode(2) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3)) OR (NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7)) OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7))); N91/N91_D2 <= ((NOT cctl AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT adr(1))); FDCPE_cfg_bank213: FDCPE port map (cfg_bank2(13),cfg_bank2_D(13),NOT phi2short,'0','0'); cfg_bank2_D(13) <= ((data(0).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (cfg_bank2(13) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); FDCPE_cfg_bank214: FDCPE port map (cfg_bank2(14),cfg_bank2_D(14),NOT phi2short,'0','0'); cfg_bank2_D(14) <= ((cfg_bank2(14) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (data(1).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); FDCPE_cfg_bank215: FDCPE port map (cfg_bank2(15),cfg_bank2_D(15),NOT phi2short,'0','0'); cfg_bank2_D(15) <= ((cfg_bank2(15) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (data(2).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); FDCPE_cfg_bank216: FDCPE port map (cfg_bank2(16),cfg_bank2_D(16),NOT phi2short,'0','0'); cfg_bank2_D(16) <= ((cfg_bank2(16) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (data(3).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); FDCPE_cfg_bank217: FDCPE port map (cfg_bank2(17),cfg_bank2_D(17),NOT phi2short,'0','0'); cfg_bank2_D(17) <= ((cfg_bank2(17) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (data(4).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); FDCPE_cfg_bank218: FDCPE port map (cfg_bank2(18),cfg_bank2_D(18),NOT phi2short,'0','0'); cfg_bank2_D(18) <= ((cfg_bank2(18) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (data(5).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); FDCPE_cfg_bank219: FDCPE port map (cfg_bank2(19),cfg_bank2_D(19),NOT phi2short,'0','0'); cfg_bank2_D(19) <= ((cfg_bank2(19) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (data(6).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); FDCPE_cfg_bank220: FDCPE port map (cfg_bank2(20),cfg_bank2_D(20),NOT phi2short,'0','0'); cfg_bank2_D(20) <= ((cfg_bank2(20) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (data(7).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); FDCPE_cfg_bank221: FDCPE port map (cfg_bank2(21),cfg_bank2_D(21),NOT phi2short,'0','0'); cfg_bank2_D(21) <= ((cfg_bank2(21) AND NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2) OR (data(0).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)); FDCPE_cfg_bank222: FDCPE port map (cfg_bank2(22),cfg_bank2_D(22),NOT phi2short,'0','0'); cfg_bank2_D(22) <= ((cfg_bank2(22) AND NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2) OR (data(1).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)); FDCPE_cfg_bank223: FDCPE port map (cfg_bank2(23),cfg_bank2_D(23),NOT phi2short,'0','0'); cfg_bank2_D(23) <= ((cfg_bank2(23) AND NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2) OR (data(2).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)); FDCPE_cfg_bank224: FDCPE port map (cfg_bank2(24),cfg_bank2_D(24),NOT phi2short,'0','0'); cfg_bank2_D(24) <= ((cfg_bank2(24) AND NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2) OR (data(3).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)); FDCPE_cfg_bank225: FDCPE port map (cfg_bank2(25),cfg_bank2_D(25),NOT phi2short,'0','0'); cfg_bank2_D(25) <= ((cfg_bank2(25) AND NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2) OR (data(4).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)); FDCPE_cfg_bank226: FDCPE port map (cfg_bank2(26),cfg_bank2_D(26),NOT phi2short,'0','0'); cfg_bank2_D(26) <= ((cfg_bank2(26) AND NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2) OR (data(5).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)); FDCPE_cfg_bank13: FDCPE port map (cfg_bank(13),cfg_bank_D(13),NOT phi2short,'0','0'); cfg_bank_D(13) <= ((EXP20_.EXP) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT adr(7) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(1) AND cfg_mode(0) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(1) AND cfg_mode(3) AND NOT adr(4) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(0) AND cfg_mode(3) AND adr(5) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND NOT cfg_mode(3) AND adr(4) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (cfg_bank2(13).EXP) OR (rw AND NOT cctl AND cfg_mode(5) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT adr(2) AND NOT adr(0) AND NOT adr(1) AND data(0).PIN AND reset_n_sync AND $OpTx$FX_DC$185) OR (rw AND NOT cctl AND cfg_mode(2) AND NOT cfg_mode(0) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(1) AND adr(7) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (reset_n_sync AND cfg_bank(13) AND NOT N91/N91_D2) OR (NOT cctl AND cfg_mode(2) AND cfg_mode(1) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(5) AND NOT cfg_mode(4) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208 AND $OpTx$FX_DC$244)); FDCPE_cfg_bank14: FDCPE port map (cfg_bank(14),cfg_bank_D(14),NOT phi2short,'0','0'); cfg_bank_D(14) <= ((NOT rw AND NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(1).PIN AND reset_n_sync AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND adr(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND cfg_mode(1) AND cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND adr(1) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (rom_ce_OBUF.EXP) OR (NOT rw AND NOT cctl AND cfg_mode(5) AND cfg_mode(4) AND data(1).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208 AND NOT $OpTx$FX_DC$164) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND adr(4) AND reset_n_sync AND cfg_bank(14) AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND NOT adr(1) AND reset_n_sync AND NOT $OpTx$FX_DC$208 AND use_cart_logic/N230/use_cart_logic/N230_D2) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(0).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(0).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208) OR (reset_n_sync AND cfg_bank(14) AND NOT N91/N91_D2) OR (NOT cctl AND reset_n_sync AND cfg_bank(14) AND NOT $OpTx$FX_DC$208 AND NOT $OpTx$INV$144) OR (NOT adr(2) AND NOT adr(0) AND NOT adr(1) AND data(1).PIN AND reset_n_sync AND $OpTx$FX_DC$185) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND reset_n_sync AND cfg_bank(14) AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT adr(7) AND reset_n_sync AND cfg_bank(14) AND NOT $OpTx$FX_DC$208)); FDCPE_cfg_bank15: FDCPE port map (cfg_bank(15),cfg_bank_D(15),NOT phi2short,'0','0'); cfg_bank_D(15) <= ((NOT cctl AND NOT adr(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND reset_n_sync AND NOT $OpTx$FX_DC$208 AND use_cart_logic/N230/use_cart_logic/N230_D2) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND adr(4) AND reset_n_sync AND cfg_bank(15) AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND data(2).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND cfg_mode(4) AND data(2).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(0) AND cfg_mode(4) AND data(2).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR ($OpTx$FX_DC$208.EXP) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(1).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(5) AND cfg_mode(1) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(1).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(2).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND adr(2) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND cfg_mode(1) AND cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND adr(1) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (reset_n_sync AND cfg_bank(15) AND NOT N91/N91_D2) OR (NOT cctl AND reset_n_sync AND cfg_bank(15) AND NOT $OpTx$FX_DC$208 AND NOT $OpTx$INV$144) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(4) AND reset_n_sync AND cfg_bank(15) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT adr(7) AND reset_n_sync AND cfg_bank(15) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(15) AND NOT $OpTx$FX_DC$208)); FDCPE_cfg_bank16: FDCPE port map (cfg_bank(16),cfg_bank_D(16),NOT phi2short,'0','0'); cfg_bank_D(16) <= ((cfg_bank2(26).EXP) OR (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND cfg_mode(1) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND cfg_mode(1) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND cfg_mode(1) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(0) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (cart_mem_adr(26).EXP) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND NOT cfg_mode(3) AND adr(4) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208 AND NOT $OpTx$FX_DC$158) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND data(3).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(2).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (cfg_bank(16) AND $OpTx$FX_DC$211) OR (rw AND NOT cctl AND cfg_mode(2) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (rw AND NOT cctl AND cfg_mode(4) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (rw AND NOT cctl AND cfg_mode(3) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208)); FDCPE_cfg_bank17: FDCPE port map (cfg_bank(17),cfg_bank_D(17),NOT phi2short,'0','0'); cfg_bank_D(17) <= ((NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND data(4).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(3).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND cfg_mode(0) AND cfg_mode(4) AND data(4).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND adr(3) AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (cfg_lock.EXP) OR (rw AND NOT cctl AND cfg_mode(5) AND cfg_mode(0) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND cfg_mode(1) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND cfg_mode(1) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(4) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(1) AND NOT cfg_mode(0) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (cfg_bank(17) AND $OpTx$FX_DC$211) OR (rw AND NOT cctl AND cfg_mode(2) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208)); FDCPE_cfg_bank18: FDCPE port map (cfg_bank(18),cfg_bank_D(18),NOT phi2short,'0','0'); cfg_bank_D(18) <= ((NOT cctl AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND adr(4) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND cfg_mode(1) AND cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND adr(5) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND data(5).PIN AND adr(5) AND NOT adr(4) AND reset_n_sync) OR (NOT rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND data(4).PIN AND NOT adr(5) AND reset_n_sync AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND reset_n_sync AND cfg_bank(18) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND cfg_mode(1) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(18) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(4) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(18) AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND data(5).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(4).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208) OR (cfg_bank(18) AND $OpTx$FX_DC$211) OR (rw AND NOT cctl AND cfg_mode(2) AND reset_n_sync AND cfg_bank(18) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND reset_n_sync AND cfg_bank(18) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(18) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(1) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(18) AND NOT $OpTx$FX_DC$208)); FDCPE_cfg_bank19: FDCPE port map (cfg_bank(19),cfg_bank_D(19),NOT phi2short,'0','0'); cfg_bank_D(19) <= ((ram_rom_data_6_IOBUFE$BUF0.EXP) OR (rw AND NOT cctl AND cfg_mode(2) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND adr(7) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT adr(2) AND NOT adr(0) AND NOT adr(1) AND data(6).PIN AND reset_n_sync AND $OpTx$FX_DC$185) OR (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(0) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(0) AND cfg_mode(4) AND data(6).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$221) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(1) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(1) AND NOT cfg_mode(4) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(0) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208)); FDCPE_cfg_bank20: FDCPE port map (cfg_bank(20),cfg_bank_D(20),NOT phi2short,'0','0'); cfg_bank_D(20) <= ((rw AND NOT cctl AND cfg_mode(2) AND reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND adr(7) AND reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$208) OR (NOT adr(2) AND NOT adr(0) AND NOT adr(1) AND data(7).PIN AND reset_n_sync AND $OpTx$FX_DC$185) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(6).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND adr(6) AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$221) OR (NOT cctl AND NOT cfg_mode(5) AND reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$208 AND NOT $OpTx$FX_DC$217) OR (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(0) AND reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(0) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$208)); FDCPE_cfg_bank21: FDCPE port map (cfg_bank(21),cfg_bank_D(21),NOT phi2short,'0','0'); cfg_bank_D(21) <= ((cfg_bank(21) AND NOT use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2) OR (data(0).PIN AND reset_n_sync AND use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2)); FDCPE_cfg_bank22: FDCPE port map (cfg_bank(22),cfg_bank_D(22),NOT phi2short,'0','0'); cfg_bank_D(22) <= ((cfg_bank(22) AND NOT use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2) OR (data(1).PIN AND reset_n_sync AND use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2)); FDCPE_cfg_bank23: FDCPE port map (cfg_bank(23),cfg_bank_D(23),NOT phi2short,'0','0'); cfg_bank_D(23) <= ((cfg_bank(23) AND NOT use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2) OR (data(2).PIN AND reset_n_sync AND use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2)); FDCPE_cfg_bank24: FDCPE port map (cfg_bank(24),cfg_bank_D(24),NOT phi2short,'0','0'); cfg_bank_D(24) <= ((cfg_bank(24) AND NOT use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2) OR (data(3).PIN AND reset_n_sync AND use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2)); FDCPE_cfg_bank25: FDCPE port map (cfg_bank(25),cfg_bank_D(25),NOT phi2short,'0','0'); cfg_bank_D(25) <= ((cfg_bank(25) AND NOT use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2) OR (data(4).PIN AND reset_n_sync AND use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2)); FDCPE_cfg_bank26: FDCPE port map (cfg_bank(26),cfg_bank_D(26),NOT phi2short,'0','0'); cfg_bank_D(26) <= ((cfg_bank(26) AND NOT use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2) OR (data(5).PIN AND reset_n_sync AND use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2)); FDCPE_cfg_enable: FDCPE port map (cfg_enable,cfg_enable_D,NOT phi2short,'0','0'); cfg_enable_D <= ((cart_mem_adr(15).EXP) OR (adr(3) AND cfg_enable AND $OpTx$FX_DC$208) OR (NOT adr(2) AND NOT adr(1) AND $OpTx$FX_DC$185) OR (data(0).PIN AND $OpTx$FX_DC$185 AND $OpTx$FX_DC$241) OR (rw AND cfg_mode(2) AND NOT cfg_mode(0) AND cfg_enable) OR (rw AND cfg_mode(5) AND cfg_enable AND NOT $OpTx$FX_DC$209) OR (NOT reset_n_sync) OR (EXP26_.EXP) OR (cctl AND cfg_enable) OR (rw AND cfg_enable AND $OpTx$FX_DC$208) OR (cfg_enable AND $OpTx$FX_DC$208 AND NOT $OpTx$FX_DC$241) OR (NOT cfg_mode(5) AND cfg_mode(1) AND cfg_mode(3) AND NOT adr(5) AND cfg_enable AND NOT $OpTx$FX_DC$208) OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT adr(7) AND cfg_enable AND NOT $OpTx$FX_DC$208) OR (NOT cfg_mode(5) AND cfg_mode(1) AND NOT cfg_mode(0) AND NOT adr(4) AND cfg_enable AND NOT $OpTx$FX_DC$208) OR (NOT cfg_mode(5) AND cfg_mode(0) AND cfg_mode(3) AND adr(5) AND cfg_enable AND NOT $OpTx$FX_DC$208) OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND adr(7) AND adr(4) AND cfg_enable AND NOT $OpTx$FX_DC$208) OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND cfg_mode(3) AND NOT adr(5) AND NOT adr(4) AND cfg_enable AND NOT $OpTx$FX_DC$208)); FTCPE_cfg_enable2: FTCPE port map (cfg_enable2,cfg_enable2_T,NOT phi2short,'0','0'); cfg_enable2_T <= ((adr(2) AND adr(0) AND cfg_enable2 AND NOT adr(1) AND NOT data(0).PIN AND $OpTx$FX_DC$185) OR (adr(2) AND NOT adr(0) AND NOT cfg_enable2 AND NOT adr(1) AND reset_n_sync AND $OpTx$FX_DC$185) OR (cfg_enable2 AND NOT reset_n_sync) OR (adr(2) AND NOT cfg_enable2 AND NOT adr(1) AND data(0).PIN AND reset_n_sync AND $OpTx$FX_DC$185) OR (NOT adr(2) AND adr(0) AND NOT cfg_enable2 AND adr(1) AND reset_n_sync AND $OpTx$FX_DC$185)); FDCPE_cfg_mode0: FDCPE port map (cfg_mode(0),cfg_mode_D(0),NOT phi2short,'0','0'); cfg_mode_D(0) <= ((NOT cfg_mode(0) AND NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2) OR (NOT data(0).PIN AND reset_n_sync AND use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)); FDCPE_cfg_mode1: FDCPE port map (cfg_mode(1),cfg_mode_D(1),NOT phi2short,'0','0'); cfg_mode_D(1) <= ((cfg_mode(1) AND NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2) OR (data(1).PIN AND reset_n_sync AND use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)); FDCPE_cfg_mode2: FDCPE port map (cfg_mode(2),cfg_mode_D(2),NOT phi2short,'0','0'); cfg_mode_D(2) <= ((cfg_mode(2) AND NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2) OR (data(2).PIN AND reset_n_sync AND use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)); FDCPE_cfg_mode3: FDCPE port map (cfg_mode(3),cfg_mode_D(3),NOT phi2short,'0','0'); cfg_mode_D(3) <= ((cfg_mode(3) AND NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2) OR (data(3).PIN AND reset_n_sync AND use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)); FDCPE_cfg_mode4: FDCPE port map (cfg_mode(4),cfg_mode_D(4),NOT phi2short,'0','0'); cfg_mode_D(4) <= ((cfg_mode(4) AND NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2) OR (data(4).PIN AND reset_n_sync AND use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)); FDCPE_cfg_mode5: FDCPE port map (cfg_mode(5),cfg_mode_D(5),NOT phi2short,'0','0'); cfg_mode_D(5) <= ((cfg_mode(5) AND NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2) OR (data(5).PIN AND reset_n_sync AND use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)); FDCPE_cfg_source_ram: FDCPE port map (cfg_source_ram,cfg_source_ram_D,NOT phi2short,'0','0'); cfg_source_ram_D <= ((cfg_source_ram AND NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2) OR (data(1).PIN AND reset_n_sync AND use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)); FDCPE_cfg_source_ram2: FDCPE port map (cfg_source_ram2,cfg_source_ram2_D,NOT phi2short,'0','0'); cfg_source_ram2_D <= ((cfg_source_ram2 AND NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2) OR (data(3).PIN AND reset_n_sync AND use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)); FDCPE_cfg_write_enable: FDCPE port map (cfg_write_enable,cfg_write_enable_D,NOT phi2short,'0','0'); cfg_write_enable_D <= ((cfg_write_enable AND NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2) OR (data(0).PIN AND reset_n_sync AND use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)); FDCPE_cfg_write_enable2: FDCPE port map (cfg_write_enable2,cfg_write_enable2_D,NOT phi2short,'0','0'); cfg_write_enable2_D <= ((cfg_write_enable2 AND NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2) OR (data(2).PIN AND reset_n_sync AND use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)); data_I(0) <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND adr(0) AND NOT mod_en AND cfg_enable2 AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_mode(0) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_bank2(21) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank(21) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND adr(0) AND NOT mod_en AND cfg_write_enable AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(13) AND data_or0000/data_or0000_D2) OR (ram_rom_data(0).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND cfg_bank(14) AND $OpTx$FX_DC$149 AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(13) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND cfg_enable AND data_or0000/data_or0000_D2)); data(0) <= data_I(0) when data_OE(0) = '1' else 'Z'; data_OE(0) <= data_7_IOBUFE/data_7_IOBUFE_TRST; data_I(1) <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND adr(0) AND NOT mod_en AND cfg_source_ram AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_mode(1) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_bank2(22) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(14) AND data_or0000/data_or0000_D2) OR (ram_rom_data(1).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND cfg_bank(15) AND $OpTx$FX_DC$149 AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(14) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank(22) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2)); data(1) <= data_I(1) when data_OE(1) = '1' else 'Z'; data_OE(1) <= data_7_IOBUFE/data_7_IOBUFE_TRST; data_I(2) <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND adr(0) AND NOT mod_en AND cfg_write_enable2 AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_mode(2) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_bank2(23) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(15) AND data_or0000/data_or0000_D2) OR (ram_rom_data(2).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND cfg_bank(16) AND $OpTx$FX_DC$149 AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(15) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank(23) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2)); data(2) <= data_I(2) when data_OE(2) = '1' else 'Z'; data_OE(2) <= data_7_IOBUFE/data_7_IOBUFE_TRST; data_I(3) <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND adr(0) AND NOT mod_en AND cfg_source_ram2 AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_mode(3) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_bank2(24) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(16) AND data_or0000/data_or0000_D2) OR (ram_rom_data(3).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND cfg_bank(17) AND $OpTx$FX_DC$149 AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(16) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank(24) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2)); data(3) <= data_I(3) when data_OE(3) = '1' else 'Z'; data_OE(3) <= data_7_IOBUFE/data_7_IOBUFE_TRST; data_I(4) <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_mode(4) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_bank2(25) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(17) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank(25) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(17) AND data_or0000/data_or0000_D2) OR (ram_rom_data(4).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND cfg_bank(18) AND $OpTx$FX_DC$149 AND data_or0000/data_or0000_D2)); data(4) <= data_I(4) when data_OE(4) = '1' else 'Z'; data_OE(4) <= data_7_IOBUFE/data_7_IOBUFE_TRST; data_I(5) <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_mode(5) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_bank2(26) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank(26) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(18) AND data_or0000/data_or0000_D2) OR (ram_rom_data(5).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND sic_8xxx_enable AND NOT adr(7) AND NOT adr(5) AND $OpTx$FX_DC$149 AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(18) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2)); data(5) <= data_I(5) when data_OE(5) = '1' else 'Z'; data_OE(5) <= data_7_IOBUFE/data_7_IOBUFE_TRST; data_I(6) <= ((ram_rom_data(6).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT sic_axxx_enable AND NOT adr(7) AND NOT adr(5) AND $OpTx$FX_DC$149 AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(19) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(19) AND data_or0000/data_or0000_D2)); data(6) <= data_I(6) when data_OE(6) = '1' else 'Z'; data_OE(6) <= data_7_IOBUFE/data_7_IOBUFE_TRST; data_I(7) <= ((rw AND NOT cctl AND NOT adr(6) AND adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND eeprom_so AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(20) AND data_or0000/data_or0000_D2) OR (ram_rom_data(7).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(20) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2)); data(7) <= data_I(7) when data_OE(7) = '1' else 'Z'; data_OE(7) <= data_7_IOBUFE/data_7_IOBUFE_TRST; data_7_IOBUFE/data_7_IOBUFE_TRST <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND phi2 AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4)) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND phi2 AND NOT adr(7) AND NOT adr(5) AND $OpTx$FX_DC$149) OR (rw AND phi2 AND use_cart_logic/N117/use_cart_logic/N117_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT mod_en AND phi2 AND adr(7) AND adr(5) AND NOT adr(4))); data_or0000/data_or0000_D2 <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT mod_en AND adr(7) AND adr(5) AND NOT adr(4)) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4)) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND $OpTx$FX_DC$149)); FDCPE_eeprom_cs: FDCPE port map (eeprom_cs,eeprom_cs_D,NOT phi2short,'0','0'); eeprom_cs_D <= ((NOT eeprom_cs AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2) OR (NOT data(1).PIN AND reset_n_sync AND use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)); FDCPE_eeprom_sck: FDCPE port map (eeprom_sck,eeprom_sck_D,NOT phi2short,'0','0'); eeprom_sck_D <= ((eeprom_sck AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2) OR (data(0).PIN AND reset_n_sync AND use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)); FDCPE_eeprom_si: FDCPE port map (eeprom_si,eeprom_si_D,NOT phi2short,'0','0'); eeprom_si_D <= ((NOT eeprom_si AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2) OR (NOT data(7).PIN AND reset_n_sync AND use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)); FDCPE_mod_en: FDCPE port map (mod_en,mod_en_D,NOT phi2short,'0','0'); mod_en_D <= ((mod_en AND reset_n_sync) OR (NOT rw AND NOT cctl AND NOT adr(6) AND adr(3) AND adr(2) AND adr(0) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND reset_n_sync)); ram_ce <= NOT (((NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND cfg_source_ram2 AND NOT s4 AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$277) OR (cfg_source_ram AND NOT $OpTx$FX_DC$277 AND source_ram_or0000/source_ram_or0000_D2) OR (NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND cfg_source_ram AND s4 AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$277))); ram_rom_adr(0) <= adr(0); ram_rom_adr(1) <= adr(1); ram_rom_adr(2) <= adr(2); ram_rom_adr(3) <= adr(3); ram_rom_adr(4) <= adr(4); ram_rom_adr(5) <= adr(5); ram_rom_adr(6) <= adr(6); ram_rom_adr(7) <= adr(7); ram_rom_adr(8) <= adr(8); ram_rom_adr(9) <= adr(9); ram_rom_adr(10) <= adr(10); ram_rom_adr(11) <= adr(11); ram_rom_adr(12) <= ((NOT use_cart_logic/oss_bank(0) AND NOT use_cart_logic/oss_bank(1) AND adr(12)) OR (cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND use_cart_logic/oss_bank(0) AND NOT adr(12) AND $OpTx$FX_DC$149) OR (NOT cfg_mode(2) AND adr(12)) OR (cfg_mode(5) AND adr(12)) OR (cfg_mode(4) AND adr(12)) OR (cfg_mode(3) AND adr(12)) OR (adr(12) AND NOT $OpTx$FX_DC$149)); ram_rom_adr(13) <= ((cfg_mode(2) AND NOT cfg_mode(3) AND cfg_bank(13) AND NOT $OpTx$FX_DC$149) OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND s4) OR (NOT cfg_mode(5) AND NOT use_cart_logic/oss_bank(0) AND NOT use_cart_logic/oss_bank(1) AND cfg_bank(13)) OR (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND s4 AND $OpTx$FX_DC$149) OR (NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND s4 AND NOT $OpTx$FX_DC$149) OR (cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND use_cart_logic/oss_bank(1) AND NOT adr(12) AND $OpTx$FX_DC$149) OR (NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND cfg_bank2(13) AND NOT s4 AND $OpTx$FX_DC$149) OR (cfg_mode(4) AND cfg_bank(13)) OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND cfg_bank(13)) OR (cfg_mode(5) AND s4 AND cfg_bank(13)) OR (NOT cfg_mode(5) AND cfg_mode(3) AND cfg_bank(13)) OR (cfg_mode(5) AND cfg_mode(4) AND NOT s5 AND NOT $OpTx$FX_DC$164)); ram_rom_adr(14) <= ((cfg_bank2(14) AND $OpTx$FX_DC$173) OR (cfg_mode(5) AND cfg_mode(4) AND NOT s5 AND NOT $OpTx$FX_DC$164) OR (cfg_bank(14) AND NOT $OpTx$FX_DC$173)); ram_rom_adr(15) <= ((cfg_bank2(15) AND $OpTx$FX_DC$173) OR (cfg_bank(15) AND NOT $OpTx$FX_DC$173) OR (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND NOT s5) OR (NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND NOT s5 AND NOT $OpTx$FX_DC$149)); ram_rom_adr(16) <= ((cfg_bank2(16) AND $OpTx$FX_DC$173) OR (cfg_bank(16) AND NOT $OpTx$FX_DC$173) OR (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND NOT s5) OR (NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND cfg_mode(4) AND NOT s5)); ram_rom_adr(17) <= ((cfg_bank2(17) AND $OpTx$FX_DC$173) OR (cfg_bank(17) AND NOT $OpTx$FX_DC$173) OR (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND NOT s5) OR (NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND cfg_mode(0) AND cfg_mode(4) AND NOT s5)); ram_rom_adr(18) <= ((cfg_bank2(18) AND $OpTx$FX_DC$173) OR (cfg_bank(18) AND NOT $OpTx$FX_DC$173) OR (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND NOT s5)); ram_rom_adr(19) <= ((cfg_bank2(19) AND $OpTx$FX_DC$173) OR (cfg_bank(19) AND NOT $OpTx$FX_DC$173) OR (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(0) AND cfg_mode(4) AND NOT s5)); ram_rom_adr(20) <= ((cfg_bank2(20) AND $OpTx$FX_DC$173) OR (cfg_bank(20) AND NOT $OpTx$FX_DC$173)); ram_rom_adr(21) <= ((cfg_bank2(21) AND $OpTx$FX_DC$173) OR (cfg_bank(21) AND NOT $OpTx$FX_DC$173)); ram_rom_adr(22) <= ((cfg_bank2(22) AND $OpTx$FX_DC$173) OR (cfg_bank(22) AND NOT $OpTx$FX_DC$173)); ram_rom_adr(23) <= ((cfg_bank2(23) AND $OpTx$FX_DC$173) OR (cfg_bank(23) AND NOT $OpTx$FX_DC$173)); ram_rom_adr(24) <= ((cfg_bank2(24) AND $OpTx$FX_DC$173) OR (cfg_bank(24) AND NOT $OpTx$FX_DC$173)); ram_rom_adr(25) <= ((cfg_bank2(25) AND $OpTx$FX_DC$173) OR (cfg_bank(25) AND NOT $OpTx$FX_DC$173)); ram_rom_adr(26) <= ((cfg_bank2(26) AND $OpTx$FX_DC$173) OR (cfg_bank(26) AND NOT $OpTx$FX_DC$173)); ram_rom_data_I(0) <= data(0).PIN; ram_rom_data(0) <= ram_rom_data_I(0) when ram_rom_data_OE(0) = '1' else 'Z'; ram_rom_data_OE(0) <= NOT rw; ram_rom_data_I(1) <= data(1).PIN; ram_rom_data(1) <= ram_rom_data_I(1) when ram_rom_data_OE(1) = '1' else 'Z'; ram_rom_data_OE(1) <= NOT rw; ram_rom_data_I(2) <= data(2).PIN; ram_rom_data(2) <= ram_rom_data_I(2) when ram_rom_data_OE(2) = '1' else 'Z'; ram_rom_data_OE(2) <= NOT rw; ram_rom_data_I(3) <= data(3).PIN; ram_rom_data(3) <= ram_rom_data_I(3) when ram_rom_data_OE(3) = '1' else 'Z'; ram_rom_data_OE(3) <= NOT rw; ram_rom_data_I(4) <= data(4).PIN; ram_rom_data(4) <= ram_rom_data_I(4) when ram_rom_data_OE(4) = '1' else 'Z'; ram_rom_data_OE(4) <= NOT rw; ram_rom_data_I(5) <= data(5).PIN; ram_rom_data(5) <= ram_rom_data_I(5) when ram_rom_data_OE(5) = '1' else 'Z'; ram_rom_data_OE(5) <= NOT rw; ram_rom_data_I(6) <= data(6).PIN; ram_rom_data(6) <= ram_rom_data_I(6) when ram_rom_data_OE(6) = '1' else 'Z'; ram_rom_data_OE(6) <= NOT rw; ram_rom_data_I(7) <= data(7).PIN; ram_rom_data(7) <= ram_rom_data_I(7) when ram_rom_data_OE(7) = '1' else 'Z'; ram_rom_data_OE(7) <= NOT rw; ram_rom_oe <= NOT ((rw AND phi2)); ram_rom_we <= NOT ((NOT rw AND phi2short)); rd4 <= ((NOT cfg_mode(2) AND cfg_mode(5) AND cfg_enable AND NOT $OpTx$FX_DC$149) OR (cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND cfg_enable) OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND cfg_enable) OR (cfg_mode(2) AND cfg_mode(5) AND sic_8xxx_enable AND cfg_enable AND $OpTx$FX_DC$149) OR (NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND cfg_enable2 AND $OpTx$FX_DC$149)); rd5 <= ((NOT cfg_mode(2) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND cfg_enable) OR (NOT cfg_mode(2) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND cfg_enable AND NOT $OpTx$FX_DC$149) OR (cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND sic_axxx_enable AND cfg_enable) OR (cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND use_cart_logic/oss_bank(0) AND cfg_enable) OR (cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND use_cart_logic/oss_bank(1) AND cfg_enable) OR (NOT cfg_mode(2) AND cfg_mode(5) AND cfg_enable) OR (cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND cfg_enable) OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND cfg_enable) OR (NOT cfg_mode(1) AND NOT cfg_mode(4) AND cfg_mode(3) AND cfg_enable)); FDCPE_reset_n_sync: FDCPE port map (reset_n_sync,reset_n_sync1,NOT phi2short,'0','0'); FDCPE_reset_n_sync1: FDCPE port map (reset_n_sync1,reset_n,NOT phi2short,'0','0'); rom_ce <= (($OpTx$FX_DC$277) OR (cfg_bank2(22).EXP) OR (NOT rw AND cfg_mode(2) AND NOT source_ram_or0000/source_ram_or0000_D2) OR (NOT rw AND NOT cfg_mode(5) AND NOT source_ram_or0000/source_ram_or0000_D2) OR (NOT rw AND cfg_mode(4) AND NOT source_ram_or0000/source_ram_or0000_D2) OR (NOT rw AND cfg_mode(3) AND NOT source_ram_or0000/source_ram_or0000_D2) OR (NOT rw AND NOT $OpTx$FX_DC$149 AND NOT source_ram_or0000/source_ram_or0000_D2) OR (cfg_source_ram AND source_ram_or0000/source_ram_or0000_D2)); FDCPE_rom_reset: FDCPE port map (rom_reset,'1',NOT phi2short,'0','0',reset_n_sync); FDCPE_sic_8xxx_enable: FDCPE port map (sic_8xxx_enable,sic_8xxx_enable_D,NOT phi2short,'0','0'); sic_8xxx_enable_D <= ((sic_8xxx_enable AND reset_n_sync AND NOT $OpTx$FX_DC$207) OR (data(5).PIN AND reset_n_sync AND $OpTx$FX_DC$207)); FDCPE_sic_axxx_enable: FDCPE port map (sic_axxx_enable,sic_axxx_enable_D,NOT phi2short,'0','0'); sic_axxx_enable_D <= ((NOT sic_axxx_enable AND reset_n_sync AND NOT $OpTx$FX_DC$207) OR (data(6).PIN AND reset_n_sync AND $OpTx$FX_DC$207)); source_ram_or0000/source_ram_or0000_D2 <= ((NOT cfg_mode(2) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$164) OR (cfg_mode(5) AND cfg_mode(4) AND NOT $OpTx$FX_DC$164) OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3)) OR (cfg_mode(2) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT $OpTx$FX_DC$164) OR (NOT cfg_mode(1) AND NOT cfg_mode(4) AND cfg_mode(3) AND NOT $OpTx$FX_DC$164) OR (NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND NOT $OpTx$FX_DC$164)); use_cart_logic/N117/use_cart_logic/N117_D2 <= ((rd4_OBUF.EXP) OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND NOT s4 AND cfg_enable) OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND cfg_enable AND NOT s5) OR (NOT cfg_mode(1) AND NOT cfg_mode(4) AND cfg_mode(3) AND cfg_enable AND NOT s5) OR (cfg_mode(2) AND cfg_mode(5) AND sic_axxx_enable AND cfg_enable AND NOT s5 AND $OpTx$FX_DC$149) OR (NOT cfg_mode(2) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND cfg_enable AND NOT s5) OR (NOT cfg_mode(2) AND cfg_mode(5) AND s4 AND cfg_enable AND NOT s5) OR (NOT cfg_mode(2) AND cfg_mode(5) AND NOT s4 AND cfg_enable AND NOT $OpTx$FX_DC$149) OR (cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND NOT s4 AND cfg_enable) OR (cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND cfg_enable AND NOT s5)); use_cart_logic/N230/use_cart_logic/N230_D2 <= ((adr(6) AND NOT cfg_mode(2) AND cfg_mode(1) AND NOT cfg_mode(0) AND NOT adr(7) AND adr(5) AND adr(4)) OR (adr(6) AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND cfg_mode(0) AND adr(7) AND NOT adr(5) AND adr(4)) OR (adr(6) AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND adr(7) AND adr(5) AND NOT adr(4))); use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2 <= ((NOT reset_n_sync) OR (NOT adr(2) AND adr(0) AND adr(1) AND $OpTx$FX_DC$185)); use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2 <= ((NOT reset_n_sync) OR (adr(2) AND NOT adr(0) AND NOT adr(1) AND $OpTx$FX_DC$185)); use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2 <= ((NOT reset_n_sync) OR (NOT adr(2) AND adr(0) AND NOT adr(1) AND $OpTx$FX_DC$185)); use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2 <= ((NOT reset_n_sync) OR (adr(2) AND NOT adr(0) AND adr(1) AND $OpTx$FX_DC$185)); use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 <= ((NOT reset_n_sync) OR (adr(2) AND adr(0) AND adr(1) AND $OpTx$FX_DC$185)); FDCPE_use_cart_logic/oss_bank0: FDCPE port map (use_cart_logic/oss_bank(0),use_cart_logic/oss_bank_D(0),NOT phi2short,'0','0'); use_cart_logic/oss_bank_D(0) <= ((use_cart_logic/oss_bank(0) AND reset_n_sync AND NOT $OpTx$FX_DC$229) OR (NOT cctl AND NOT adr(3) AND cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND reset_n_sync AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208)); FDCPE_use_cart_logic/oss_bank1: FDCPE port map (use_cart_logic/oss_bank(1),use_cart_logic/oss_bank_D(1),NOT phi2short,'0','0'); use_cart_logic/oss_bank_D(1) <= ((use_cart_logic/oss_bank(1) AND reset_n_sync AND NOT $OpTx$FX_DC$229) OR (NOT cctl AND adr(0) AND cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND reset_n_sync AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208)); use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 <= ((NOT reset_n_sync) OR (NOT rw AND NOT cctl AND NOT adr(6) AND adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4))); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95144XL-10-TQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC95144XL-10-TQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 data<4> 51 VCC 2 PGND 52 ram_rom_adr<2> 3 s4 53 ram_rom_adr<3> 4 s5 54 ram_rom_adr<4> 5 VCC 55 ram_rom_adr<5> 6 data<5> 56 ram_rom_adr<6> 7 PGND 57 VCC 8 data<2> 58 ram_rom_adr<7> 9 data<1> 59 ram_rom_adr<8> 10 data<3> 60 ram_rom_adr<18> 11 data<0> 61 ram_rom_adr<19> 12 data<7> 62 GND 13 data<6> 63 ram_rom_adr<22> 14 adr<11> 64 ram_rom_adr<21> 15 adr<10> 65 ram_rom_adr<20> 16 eeprom_cs 66 ram_rom_adr<9> 17 eeprom_so 67 ram_rom_adr<10> 18 eeprom_sck 68 ram_rom_adr<11> 19 PGND 69 GND 20 eeprom_si 70 ram_rom_adr<12> 21 GND 71 ram_rom_adr<13> 22 phi2 72 ram_rom_adr<14> 23 phi2short 73 mod_en 24 ram_rom_adr<26> 74 ram_rom_adr<15> 25 ram_rom_adr<0> 75 GND 26 VCC 76 ram_rom_adr<16> 27 cctl 77 ram_rom_adr<23> 28 ram_rom_adr<17> 78 ram_rom_adr<24> 29 ram_rom_adr<25> 79 rd5 30 rom_reset 80 PGND 31 GND 81 rd4 32 ram_rom_data<7> 82 reset_n 33 ram_rom_data<6> 83 TDO 34 PGND 84 GND 35 ram_rom_data<5> 85 ram_ce 36 ram_rom_data<4> 86 adr<3> 37 ram_rom_data<3> 87 adr<4> 38 VCC 88 VCC 39 ram_rom_data<2> 89 adr<2> 40 ram_rom_data<1> 90 adr<5> 41 ram_rom_data<0> 91 adr<1> 42 ram_rom_oe 92 adr<6> 43 ram_rom_adr<1> 93 adr<0> 44 GND 94 adr<7> 45 TDI 95 adr<8> 46 PGND 96 adr<9> 47 TMS 97 adr<12> 48 TCK 98 VCC 49 rom_ce 99 rw 50 ram_rom_we 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95144xl-10-TQ100 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : SLOW Power Mode : LOW Ground on Unused IOs : ON Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 40 Pterm Limit : 28