********** Mapped Logic ********** |
$OpTx$FX_DC$149 <= (NOT cfg_mode(1) AND NOT cfg_mode(0)); |
$OpTx$FX_DC$158 <= (NOT adr(6) AND NOT adr(5)); |
$OpTx$FX_DC$164 <= (cfg_mode(2) AND cfg_mode(1)); |
$OpTx$FX_DC$173 <= (NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND
NOT cfg_mode(3) AND NOT s4 AND $OpTx$FX_DC$149); |
$OpTx$FX_DC$185 <= (NOT rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT mod_en AND adr(7) AND
adr(5) AND NOT adr(4)); |
$OpTx$FX_DC$207 <= (NOT rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND
NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND $OpTx$FX_DC$149); |
$OpTx$FX_DC$208 <= (NOT adr(6) AND NOT mod_en AND adr(7) AND adr(5) AND NOT adr(4)); |
$OpTx$FX_DC$209 <= (NOT cfg_mode(0) AND NOT cfg_mode(3)); |
$OpTx$FX_DC$211 <= ((NOT cctl AND cfg_mode(2) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND
reset_n_sync AND NOT $OpTx$FX_DC$208 AND NOT $OpTx$FX_DC$158) OR (NOT cctl AND cfg_mode(5) AND cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (reset_n_sync AND NOT N91/N91_D2) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND adr(7) AND reset_n_sync AND NOT $OpTx$FX_DC$208)); |
$OpTx$FX_DC$217 <= (cfg_mode(1) AND NOT cfg_mode(4)); |
$OpTx$FX_DC$221 <= ((NOT cctl AND NOT $OpTx$FX_DC$208)
OR (NOT rw AND NOT cctl AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT adr(1))); |
$OpTx$FX_DC$229 <= (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND
NOT cfg_mode(3) AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208); |
$OpTx$FX_DC$241 <= (NOT adr(2) AND NOT adr(0)); |
$OpTx$FX_DC$244 <= ((NOT adr(6) AND NOT cfg_mode(2) AND cfg_mode(3))
OR (cfg_mode(2) AND cfg_mode(0) AND adr(7)) OR (cfg_mode(2) AND cfg_mode(0) AND adr(4)) OR (adr(6) AND cfg_mode(2) AND cfg_mode(0))); |
$OpTx$FX_DC$269 <= ((NOT cfg_mode(5) AND adr(4))
OR (NOT cfg_mode(5) AND NOT $OpTx$FX_DC$158)); |
$OpTx$FX_DC$277 <= ((NOT use_cart_logic/N117/use_cart_logic/N117_D2)
OR (NOT rw AND NOT cfg_write_enable2 AND NOT s4 AND NOT source_ram_or0000/source_ram_or0000_D2) OR (NOT rw AND NOT cfg_write_enable2 AND NOT cfg_write_enable) OR (NOT rw AND NOT cfg_write_enable AND NOT $OpTx$FX_DC$173)); |
$OpTx$INV$144 <= ((NOT rw AND NOT adr(6) AND cfg_mode(5) AND NOT cfg_mode(1) AND
NOT cfg_mode(0) AND NOT adr(7) AND NOT adr(5)) OR (adr(6) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND adr(5)) OR (NOT adr(6) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND NOT adr(4)) OR (adr(6) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND NOT adr(5) AND adr(4)) OR (adr(6) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND NOT adr(7) AND adr(5) AND adr(4)) OR (NOT adr(6) AND cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND NOT adr(4)) OR (NOT rw AND cfg_mode(5) AND cfg_mode(4) AND NOT $OpTx$FX_DC$164) OR (NOT rw AND cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3)) OR (NOT rw AND cfg_mode(2) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3)) OR (NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7)) OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7))); |
N91/N91_D2 <= ((NOT cctl AND NOT $OpTx$FX_DC$208)
OR (NOT rw AND NOT cctl AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT adr(1))); |
FDCPE_cfg_bank213: FDCPE port map (cfg_bank2(13),cfg_bank2_D(13),NOT phi2short,'0','0');
cfg_bank2_D(13) <= ((data(0).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (cfg_bank2(13) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); |
FDCPE_cfg_bank214: FDCPE port map (cfg_bank2(14),cfg_bank2_D(14),NOT phi2short,'0','0');
cfg_bank2_D(14) <= ((cfg_bank2(14) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (data(1).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); |
FDCPE_cfg_bank215: FDCPE port map (cfg_bank2(15),cfg_bank2_D(15),NOT phi2short,'0','0');
cfg_bank2_D(15) <= ((cfg_bank2(15) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (data(2).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); |
FDCPE_cfg_bank216: FDCPE port map (cfg_bank2(16),cfg_bank2_D(16),NOT phi2short,'0','0');
cfg_bank2_D(16) <= ((cfg_bank2(16) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (data(3).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); |
FDCPE_cfg_bank217: FDCPE port map (cfg_bank2(17),cfg_bank2_D(17),NOT phi2short,'0','0');
cfg_bank2_D(17) <= ((cfg_bank2(17) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (data(4).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); |
FDCPE_cfg_bank218: FDCPE port map (cfg_bank2(18),cfg_bank2_D(18),NOT phi2short,'0','0');
cfg_bank2_D(18) <= ((cfg_bank2(18) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (data(5).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); |
FDCPE_cfg_bank219: FDCPE port map (cfg_bank2(19),cfg_bank2_D(19),NOT phi2short,'0','0');
cfg_bank2_D(19) <= ((cfg_bank2(19) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (data(6).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); |
FDCPE_cfg_bank220: FDCPE port map (cfg_bank2(20),cfg_bank2_D(20),NOT phi2short,'0','0');
cfg_bank2_D(20) <= ((cfg_bank2(20) AND NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2) OR (data(7).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)); |
FDCPE_cfg_bank221: FDCPE port map (cfg_bank2(21),cfg_bank2_D(21),NOT phi2short,'0','0');
cfg_bank2_D(21) <= ((cfg_bank2(21) AND NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2) OR (data(0).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)); |
FDCPE_cfg_bank222: FDCPE port map (cfg_bank2(22),cfg_bank2_D(22),NOT phi2short,'0','0');
cfg_bank2_D(22) <= ((cfg_bank2(22) AND NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2) OR (data(1).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)); |
FDCPE_cfg_bank223: FDCPE port map (cfg_bank2(23),cfg_bank2_D(23),NOT phi2short,'0','0');
cfg_bank2_D(23) <= ((cfg_bank2(23) AND NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2) OR (data(2).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)); |
FDCPE_cfg_bank224: FDCPE port map (cfg_bank2(24),cfg_bank2_D(24),NOT phi2short,'0','0');
cfg_bank2_D(24) <= ((cfg_bank2(24) AND NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2) OR (data(3).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)); |
FDCPE_cfg_bank225: FDCPE port map (cfg_bank2(25),cfg_bank2_D(25),NOT phi2short,'0','0');
cfg_bank2_D(25) <= ((cfg_bank2(25) AND NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2) OR (data(4).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)); |
FDCPE_cfg_bank226: FDCPE port map (cfg_bank2(26),cfg_bank2_D(26),NOT phi2short,'0','0');
cfg_bank2_D(26) <= ((cfg_bank2(26) AND NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2) OR (data(5).PIN AND reset_n_sync AND use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)); |
FDCPE_cfg_bank13: FDCPE port map (cfg_bank(13),cfg_bank_D(13),NOT phi2short,'0','0');
cfg_bank_D(13) <= ((EXP20_.EXP) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT adr(7) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(1) AND cfg_mode(0) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(1) AND cfg_mode(3) AND NOT adr(4) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(0) AND cfg_mode(3) AND adr(5) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND NOT cfg_mode(3) AND adr(4) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (cfg_bank2(13).EXP) OR (rw AND NOT cctl AND cfg_mode(5) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT adr(2) AND NOT adr(0) AND NOT adr(1) AND data(0).PIN AND reset_n_sync AND $OpTx$FX_DC$185) OR (rw AND NOT cctl AND cfg_mode(2) AND NOT cfg_mode(0) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(1) AND adr(7) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (reset_n_sync AND cfg_bank(13) AND NOT N91/N91_D2) OR (NOT cctl AND cfg_mode(2) AND cfg_mode(1) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(5) AND NOT cfg_mode(4) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND reset_n_sync AND cfg_bank(13) AND NOT $OpTx$FX_DC$208 AND $OpTx$FX_DC$244)); |
FDCPE_cfg_bank14: FDCPE port map (cfg_bank(14),cfg_bank_D(14),NOT phi2short,'0','0');
cfg_bank_D(14) <= ((NOT rw AND NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(1).PIN AND reset_n_sync AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND adr(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND cfg_mode(1) AND cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND adr(1) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (rom_ce_OBUF.EXP) OR (NOT rw AND NOT cctl AND cfg_mode(5) AND cfg_mode(4) AND data(1).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208 AND NOT $OpTx$FX_DC$164) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND adr(4) AND reset_n_sync AND cfg_bank(14) AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND NOT adr(1) AND reset_n_sync AND NOT $OpTx$FX_DC$208 AND use_cart_logic/N230/use_cart_logic/N230_D2) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(0).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(0).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208) OR (reset_n_sync AND cfg_bank(14) AND NOT N91/N91_D2) OR (NOT cctl AND reset_n_sync AND cfg_bank(14) AND NOT $OpTx$FX_DC$208 AND NOT $OpTx$INV$144) OR (NOT adr(2) AND NOT adr(0) AND NOT adr(1) AND data(1).PIN AND reset_n_sync AND $OpTx$FX_DC$185) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND reset_n_sync AND cfg_bank(14) AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT adr(7) AND reset_n_sync AND cfg_bank(14) AND NOT $OpTx$FX_DC$208)); |
FDCPE_cfg_bank15: FDCPE port map (cfg_bank(15),cfg_bank_D(15),NOT phi2short,'0','0');
cfg_bank_D(15) <= ((NOT cctl AND NOT adr(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND reset_n_sync AND NOT $OpTx$FX_DC$208 AND use_cart_logic/N230/use_cart_logic/N230_D2) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND adr(4) AND reset_n_sync AND cfg_bank(15) AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND data(2).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND cfg_mode(4) AND data(2).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(0) AND cfg_mode(4) AND data(2).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR ($OpTx$FX_DC$208.EXP) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(1).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(5) AND cfg_mode(1) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(1).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(2).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND adr(2) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND cfg_mode(1) AND cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND adr(1) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (reset_n_sync AND cfg_bank(15) AND NOT N91/N91_D2) OR (NOT cctl AND reset_n_sync AND cfg_bank(15) AND NOT $OpTx$FX_DC$208 AND NOT $OpTx$INV$144) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(4) AND reset_n_sync AND cfg_bank(15) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT adr(7) AND reset_n_sync AND cfg_bank(15) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(15) AND NOT $OpTx$FX_DC$208)); |
FDCPE_cfg_bank16: FDCPE port map (cfg_bank(16),cfg_bank_D(16),NOT phi2short,'0','0');
cfg_bank_D(16) <= ((cfg_bank2(26).EXP) OR (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND cfg_mode(1) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND cfg_mode(1) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND cfg_mode(1) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(0) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (cart_mem_adr(26).EXP) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND NOT cfg_mode(3) AND adr(4) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208 AND NOT $OpTx$FX_DC$158) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND data(3).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(2).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (cfg_bank(16) AND $OpTx$FX_DC$211) OR (rw AND NOT cctl AND cfg_mode(2) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (rw AND NOT cctl AND cfg_mode(4) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (rw AND NOT cctl AND cfg_mode(3) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(16) AND NOT $OpTx$FX_DC$208)); |
FDCPE_cfg_bank17: FDCPE port map (cfg_bank(17),cfg_bank_D(17),NOT phi2short,'0','0');
cfg_bank_D(17) <= ((NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND data(4).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(3).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND cfg_mode(0) AND cfg_mode(4) AND data(4).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND adr(3) AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (cfg_lock.EXP) OR (rw AND NOT cctl AND cfg_mode(5) AND cfg_mode(0) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND cfg_mode(1) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND cfg_mode(1) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(4) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(1) AND NOT cfg_mode(0) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (cfg_bank(17) AND $OpTx$FX_DC$211) OR (rw AND NOT cctl AND cfg_mode(2) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(17) AND NOT $OpTx$FX_DC$208)); |
FDCPE_cfg_bank18: FDCPE port map (cfg_bank(18),cfg_bank_D(18),NOT phi2short,'0','0');
cfg_bank_D(18) <= ((NOT cctl AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND adr(4) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND cfg_mode(1) AND cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND adr(5) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND data(5).PIN AND adr(5) AND NOT adr(4) AND reset_n_sync) OR (NOT rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND data(4).PIN AND NOT adr(5) AND reset_n_sync AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND reset_n_sync AND cfg_bank(18) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND cfg_mode(1) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(18) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(4) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(18) AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND data(5).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(4).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208) OR (cfg_bank(18) AND $OpTx$FX_DC$211) OR (rw AND NOT cctl AND cfg_mode(2) AND reset_n_sync AND cfg_bank(18) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND reset_n_sync AND cfg_bank(18) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(18) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(1) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(18) AND NOT $OpTx$FX_DC$208)); |
FDCPE_cfg_bank19: FDCPE port map (cfg_bank(19),cfg_bank_D(19),NOT phi2short,'0','0');
cfg_bank_D(19) <= ((ram_rom_data_6_IOBUFE$BUF0.EXP) OR (rw AND NOT cctl AND cfg_mode(2) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(5) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND adr(7) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT adr(2) AND NOT adr(0) AND NOT adr(1) AND data(6).PIN AND reset_n_sync AND $OpTx$FX_DC$185) OR (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(0) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(0) AND cfg_mode(4) AND data(6).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$221) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(1) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(1) AND NOT cfg_mode(4) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(0) AND cfg_mode(4) AND reset_n_sync AND cfg_bank(19) AND NOT $OpTx$FX_DC$208)); |
FDCPE_cfg_bank20: FDCPE port map (cfg_bank(20),cfg_bank_D(20),NOT phi2short,'0','0');
cfg_bank_D(20) <= ((rw AND NOT cctl AND cfg_mode(2) AND reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND cfg_mode(3) AND reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND NOT cfg_mode(2) AND adr(7) AND reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$208) OR (NOT adr(2) AND NOT adr(0) AND NOT adr(1) AND data(7).PIN AND reset_n_sync AND $OpTx$FX_DC$185) OR (NOT rw AND NOT cctl AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND data(6).PIN AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND adr(6) AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND reset_n_sync AND NOT $OpTx$FX_DC$208) OR (reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$221) OR (NOT cctl AND NOT cfg_mode(5) AND reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$208 AND NOT $OpTx$FX_DC$217) OR (NOT cctl AND cfg_mode(2) AND NOT cfg_mode(0) AND reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$208) OR (NOT cctl AND cfg_mode(0) AND NOT cfg_mode(3) AND reset_n_sync AND cfg_bank(20) AND NOT $OpTx$FX_DC$208)); |
FDCPE_cfg_bank21: FDCPE port map (cfg_bank(21),cfg_bank_D(21),NOT phi2short,'0','0');
cfg_bank_D(21) <= ((cfg_bank(21) AND NOT use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2) OR (data(0).PIN AND reset_n_sync AND use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2)); |
FDCPE_cfg_bank22: FDCPE port map (cfg_bank(22),cfg_bank_D(22),NOT phi2short,'0','0');
cfg_bank_D(22) <= ((cfg_bank(22) AND NOT use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2) OR (data(1).PIN AND reset_n_sync AND use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2)); |
FDCPE_cfg_bank23: FDCPE port map (cfg_bank(23),cfg_bank_D(23),NOT phi2short,'0','0');
cfg_bank_D(23) <= ((cfg_bank(23) AND NOT use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2) OR (data(2).PIN AND reset_n_sync AND use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2)); |
FDCPE_cfg_bank24: FDCPE port map (cfg_bank(24),cfg_bank_D(24),NOT phi2short,'0','0');
cfg_bank_D(24) <= ((cfg_bank(24) AND NOT use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2) OR (data(3).PIN AND reset_n_sync AND use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2)); |
FDCPE_cfg_bank25: FDCPE port map (cfg_bank(25),cfg_bank_D(25),NOT phi2short,'0','0');
cfg_bank_D(25) <= ((cfg_bank(25) AND NOT use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2) OR (data(4).PIN AND reset_n_sync AND use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2)); |
FDCPE_cfg_bank26: FDCPE port map (cfg_bank(26),cfg_bank_D(26),NOT phi2short,'0','0');
cfg_bank_D(26) <= ((cfg_bank(26) AND NOT use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2) OR (data(5).PIN AND reset_n_sync AND use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2)); |
FDCPE_cfg_enable: FDCPE port map (cfg_enable,cfg_enable_D,NOT phi2short,'0','0');
cfg_enable_D <= ((cart_mem_adr(15).EXP) OR (adr(3) AND cfg_enable AND $OpTx$FX_DC$208) OR (NOT adr(2) AND NOT adr(1) AND $OpTx$FX_DC$185) OR (data(0).PIN AND $OpTx$FX_DC$185 AND $OpTx$FX_DC$241) OR (rw AND cfg_mode(2) AND NOT cfg_mode(0) AND cfg_enable) OR (rw AND cfg_mode(5) AND cfg_enable AND NOT $OpTx$FX_DC$209) OR (NOT reset_n_sync) OR (EXP26_.EXP) OR (cctl AND cfg_enable) OR (rw AND cfg_enable AND $OpTx$FX_DC$208) OR (cfg_enable AND $OpTx$FX_DC$208 AND NOT $OpTx$FX_DC$241) OR (NOT cfg_mode(5) AND cfg_mode(1) AND cfg_mode(3) AND NOT adr(5) AND cfg_enable AND NOT $OpTx$FX_DC$208) OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT adr(7) AND cfg_enable AND NOT $OpTx$FX_DC$208) OR (NOT cfg_mode(5) AND cfg_mode(1) AND NOT cfg_mode(0) AND NOT adr(4) AND cfg_enable AND NOT $OpTx$FX_DC$208) OR (NOT cfg_mode(5) AND cfg_mode(0) AND cfg_mode(3) AND adr(5) AND cfg_enable AND NOT $OpTx$FX_DC$208) OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(0) AND adr(7) AND adr(4) AND cfg_enable AND NOT $OpTx$FX_DC$208) OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND cfg_mode(3) AND NOT adr(5) AND NOT adr(4) AND cfg_enable AND NOT $OpTx$FX_DC$208)); |
FTCPE_cfg_enable2: FTCPE port map (cfg_enable2,cfg_enable2_T,NOT phi2short,'0','0');
cfg_enable2_T <= ((adr(2) AND adr(0) AND cfg_enable2 AND NOT adr(1) AND NOT data(0).PIN AND $OpTx$FX_DC$185) OR (adr(2) AND NOT adr(0) AND NOT cfg_enable2 AND NOT adr(1) AND reset_n_sync AND $OpTx$FX_DC$185) OR (cfg_enable2 AND NOT reset_n_sync) OR (adr(2) AND NOT cfg_enable2 AND NOT adr(1) AND data(0).PIN AND reset_n_sync AND $OpTx$FX_DC$185) OR (NOT adr(2) AND adr(0) AND NOT cfg_enable2 AND adr(1) AND reset_n_sync AND $OpTx$FX_DC$185)); |
FDCPE_cfg_mode0: FDCPE port map (cfg_mode(0),cfg_mode_D(0),NOT phi2short,'0','0');
cfg_mode_D(0) <= ((NOT cfg_mode(0) AND NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2) OR (NOT data(0).PIN AND reset_n_sync AND use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)); |
FDCPE_cfg_mode1: FDCPE port map (cfg_mode(1),cfg_mode_D(1),NOT phi2short,'0','0');
cfg_mode_D(1) <= ((cfg_mode(1) AND NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2) OR (data(1).PIN AND reset_n_sync AND use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)); |
FDCPE_cfg_mode2: FDCPE port map (cfg_mode(2),cfg_mode_D(2),NOT phi2short,'0','0');
cfg_mode_D(2) <= ((cfg_mode(2) AND NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2) OR (data(2).PIN AND reset_n_sync AND use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)); |
FDCPE_cfg_mode3: FDCPE port map (cfg_mode(3),cfg_mode_D(3),NOT phi2short,'0','0');
cfg_mode_D(3) <= ((cfg_mode(3) AND NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2) OR (data(3).PIN AND reset_n_sync AND use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)); |
FDCPE_cfg_mode4: FDCPE port map (cfg_mode(4),cfg_mode_D(4),NOT phi2short,'0','0');
cfg_mode_D(4) <= ((cfg_mode(4) AND NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2) OR (data(4).PIN AND reset_n_sync AND use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)); |
FDCPE_cfg_mode5: FDCPE port map (cfg_mode(5),cfg_mode_D(5),NOT phi2short,'0','0');
cfg_mode_D(5) <= ((cfg_mode(5) AND NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2) OR (data(5).PIN AND reset_n_sync AND use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)); |
FDCPE_cfg_source_ram: FDCPE port map (cfg_source_ram,cfg_source_ram_D,NOT phi2short,'0','0');
cfg_source_ram_D <= ((cfg_source_ram AND NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2) OR (data(1).PIN AND reset_n_sync AND use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)); |
FDCPE_cfg_source_ram2: FDCPE port map (cfg_source_ram2,cfg_source_ram2_D,NOT phi2short,'0','0');
cfg_source_ram2_D <= ((cfg_source_ram2 AND NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2) OR (data(3).PIN AND reset_n_sync AND use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)); |
FDCPE_cfg_write_enable: FDCPE port map (cfg_write_enable,cfg_write_enable_D,NOT phi2short,'0','0');
cfg_write_enable_D <= ((cfg_write_enable AND NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2) OR (data(0).PIN AND reset_n_sync AND use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)); |
FDCPE_cfg_write_enable2: FDCPE port map (cfg_write_enable2,cfg_write_enable2_D,NOT phi2short,'0','0');
cfg_write_enable2_D <= ((cfg_write_enable2 AND NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2) OR (data(2).PIN AND reset_n_sync AND use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)); |
data_I(0) <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND adr(0) AND
NOT mod_en AND cfg_enable2 AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_mode(0) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_bank2(21) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank(21) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND adr(0) AND NOT mod_en AND cfg_write_enable AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(13) AND data_or0000/data_or0000_D2) OR (ram_rom_data(0).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND cfg_bank(14) AND $OpTx$FX_DC$149 AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(13) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND cfg_enable AND data_or0000/data_or0000_D2)); data(0) <= data_I(0) when data_OE(0) = '1' else 'Z'; data_OE(0) <= data_7_IOBUFE/data_7_IOBUFE_TRST; |
data_I(1) <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND adr(0) AND
NOT mod_en AND cfg_source_ram AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_mode(1) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_bank2(22) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(14) AND data_or0000/data_or0000_D2) OR (ram_rom_data(1).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND cfg_bank(15) AND $OpTx$FX_DC$149 AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(14) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank(22) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2)); data(1) <= data_I(1) when data_OE(1) = '1' else 'Z'; data_OE(1) <= data_7_IOBUFE/data_7_IOBUFE_TRST; |
data_I(2) <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND adr(0) AND
NOT mod_en AND cfg_write_enable2 AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_mode(2) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_bank2(23) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(15) AND data_or0000/data_or0000_D2) OR (ram_rom_data(2).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND cfg_bank(16) AND $OpTx$FX_DC$149 AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(15) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank(23) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2)); data(2) <= data_I(2) when data_OE(2) = '1' else 'Z'; data_OE(2) <= data_7_IOBUFE/data_7_IOBUFE_TRST; |
data_I(3) <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND adr(0) AND
NOT mod_en AND cfg_source_ram2 AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_mode(3) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_bank2(24) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(16) AND data_or0000/data_or0000_D2) OR (ram_rom_data(3).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND cfg_bank(17) AND $OpTx$FX_DC$149 AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(16) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank(24) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2)); data(3) <= data_I(3) when data_OE(3) = '1' else 'Z'; data_OE(3) <= data_7_IOBUFE/data_7_IOBUFE_TRST; |
data_I(4) <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND
NOT mod_en AND cfg_mode(4) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_bank2(25) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(17) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank(25) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(17) AND data_or0000/data_or0000_D2) OR (ram_rom_data(4).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND cfg_bank(18) AND $OpTx$FX_DC$149 AND data_or0000/data_or0000_D2)); data(4) <= data_I(4) when data_OE(4) = '1' else 'Z'; data_OE(4) <= data_7_IOBUFE/data_7_IOBUFE_TRST; |
data_I(5) <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND
NOT mod_en AND cfg_mode(5) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT mod_en AND cfg_bank2(26) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank(26) AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(18) AND data_or0000/data_or0000_D2) OR (ram_rom_data(5).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND sic_8xxx_enable AND NOT adr(7) AND NOT adr(5) AND $OpTx$FX_DC$149 AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(18) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2)); data(5) <= data_I(5) when data_OE(5) = '1' else 'Z'; data_OE(5) <= data_7_IOBUFE/data_7_IOBUFE_TRST; |
data_I(6) <= ((ram_rom_data(6).PIN AND NOT data_or0000/data_or0000_D2)
OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT sic_axxx_enable AND NOT adr(7) AND NOT adr(5) AND $OpTx$FX_DC$149 AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(19) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(19) AND data_or0000/data_or0000_D2)); data(6) <= data_I(6) when data_OE(6) = '1' else 'Z'; data_OE(6) <= data_7_IOBUFE/data_7_IOBUFE_TRST; |
data_I(7) <= ((rw AND NOT cctl AND NOT adr(6) AND adr(3) AND NOT adr(2) AND NOT adr(0) AND
NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND eeprom_so AND data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4) AND cfg_bank(20) AND data_or0000/data_or0000_D2) OR (ram_rom_data(7).PIN AND NOT data_or0000/data_or0000_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT mod_en AND cfg_bank2(20) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND data_or0000/data_or0000_D2)); data(7) <= data_I(7) when data_OE(7) = '1' else 'Z'; data_OE(7) <= data_7_IOBUFE/data_7_IOBUFE_TRST; |
data_7_IOBUFE/data_7_IOBUFE_TRST <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND
phi2 AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4)) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND phi2 AND NOT adr(7) AND NOT adr(5) AND $OpTx$FX_DC$149) OR (rw AND phi2 AND use_cart_logic/N117/use_cart_logic/N117_D2) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT mod_en AND phi2 AND adr(7) AND adr(5) AND NOT adr(4))); |
data_or0000/data_or0000_D2 <= ((rw AND NOT cctl AND NOT adr(6) AND NOT adr(3) AND NOT mod_en AND adr(7) AND
adr(5) AND NOT adr(4)) OR (rw AND NOT cctl AND NOT adr(6) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4)) OR (rw AND NOT cctl AND NOT adr(6) AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND NOT adr(7) AND NOT adr(5) AND $OpTx$FX_DC$149)); |
FDCPE_eeprom_cs: FDCPE port map (eeprom_cs,eeprom_cs_D,NOT phi2short,'0','0');
eeprom_cs_D <= ((NOT eeprom_cs AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2) OR (NOT data(1).PIN AND reset_n_sync AND use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)); |
FDCPE_eeprom_sck: FDCPE port map (eeprom_sck,eeprom_sck_D,NOT phi2short,'0','0');
eeprom_sck_D <= ((eeprom_sck AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2) OR (data(0).PIN AND reset_n_sync AND use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)); |
FDCPE_eeprom_si: FDCPE port map (eeprom_si,eeprom_si_D,NOT phi2short,'0','0');
eeprom_si_D <= ((NOT eeprom_si AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2) OR (NOT data(7).PIN AND reset_n_sync AND use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)); |
FDCPE_mod_en: FDCPE port map (mod_en,mod_en_D,NOT phi2short,'0','0');
mod_en_D <= ((mod_en AND reset_n_sync) OR (NOT rw AND NOT cctl AND NOT adr(6) AND adr(3) AND adr(2) AND adr(0) AND adr(7) AND adr(1) AND adr(5) AND NOT adr(4) AND reset_n_sync)); |
ram_ce <= NOT (((NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND
NOT cfg_mode(3) AND cfg_source_ram2 AND NOT s4 AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$277) OR (cfg_source_ram AND NOT $OpTx$FX_DC$277 AND source_ram_or0000/source_ram_or0000_D2) OR (NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND cfg_source_ram AND s4 AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$277))); |
ram_rom_adr(0) <= adr(0); |
ram_rom_adr(1) <= adr(1); |
ram_rom_adr(2) <= adr(2); |
ram_rom_adr(3) <= adr(3); |
ram_rom_adr(4) <= adr(4); |
ram_rom_adr(5) <= adr(5); |
ram_rom_adr(6) <= adr(6); |
ram_rom_adr(7) <= adr(7); |
ram_rom_adr(8) <= adr(8); |
ram_rom_adr(9) <= adr(9); |
ram_rom_adr(10) <= adr(10); |
ram_rom_adr(11) <= adr(11); |
ram_rom_adr(12) <= ((NOT use_cart_logic/oss_bank(0) AND
NOT use_cart_logic/oss_bank(1) AND adr(12)) OR (cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND use_cart_logic/oss_bank(0) AND NOT adr(12) AND $OpTx$FX_DC$149) OR (NOT cfg_mode(2) AND adr(12)) OR (cfg_mode(5) AND adr(12)) OR (cfg_mode(4) AND adr(12)) OR (cfg_mode(3) AND adr(12)) OR (adr(12) AND NOT $OpTx$FX_DC$149)); |
ram_rom_adr(13) <= ((cfg_mode(2) AND NOT cfg_mode(3) AND cfg_bank(13) AND
NOT $OpTx$FX_DC$149) OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND s4) OR (NOT cfg_mode(5) AND NOT use_cart_logic/oss_bank(0) AND NOT use_cart_logic/oss_bank(1) AND cfg_bank(13)) OR (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND s4 AND $OpTx$FX_DC$149) OR (NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND s4 AND NOT $OpTx$FX_DC$149) OR (cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND use_cart_logic/oss_bank(1) AND NOT adr(12) AND $OpTx$FX_DC$149) OR (NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND cfg_bank2(13) AND NOT s4 AND $OpTx$FX_DC$149) OR (cfg_mode(4) AND cfg_bank(13)) OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND cfg_bank(13)) OR (cfg_mode(5) AND s4 AND cfg_bank(13)) OR (NOT cfg_mode(5) AND cfg_mode(3) AND cfg_bank(13)) OR (cfg_mode(5) AND cfg_mode(4) AND NOT s5 AND NOT $OpTx$FX_DC$164)); |
ram_rom_adr(14) <= ((cfg_bank2(14) AND $OpTx$FX_DC$173)
OR (cfg_mode(5) AND cfg_mode(4) AND NOT s5 AND NOT $OpTx$FX_DC$164) OR (cfg_bank(14) AND NOT $OpTx$FX_DC$173)); |
ram_rom_adr(15) <= ((cfg_bank2(15) AND $OpTx$FX_DC$173)
OR (cfg_bank(15) AND NOT $OpTx$FX_DC$173) OR (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND NOT s5) OR (NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND NOT s5 AND NOT $OpTx$FX_DC$149)); |
ram_rom_adr(16) <= ((cfg_bank2(16) AND $OpTx$FX_DC$173)
OR (cfg_bank(16) AND NOT $OpTx$FX_DC$173) OR (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND NOT s5) OR (NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND cfg_mode(4) AND NOT s5)); |
ram_rom_adr(17) <= ((cfg_bank2(17) AND $OpTx$FX_DC$173)
OR (cfg_bank(17) AND NOT $OpTx$FX_DC$173) OR (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND NOT s5) OR (NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND cfg_mode(0) AND cfg_mode(4) AND NOT s5)); |
ram_rom_adr(18) <= ((cfg_bank2(18) AND $OpTx$FX_DC$173)
OR (cfg_bank(18) AND NOT $OpTx$FX_DC$173) OR (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND NOT s5)); |
ram_rom_adr(19) <= ((cfg_bank2(19) AND $OpTx$FX_DC$173)
OR (cfg_bank(19) AND NOT $OpTx$FX_DC$173) OR (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(0) AND cfg_mode(4) AND NOT s5)); |
ram_rom_adr(20) <= ((cfg_bank2(20) AND $OpTx$FX_DC$173)
OR (cfg_bank(20) AND NOT $OpTx$FX_DC$173)); |
ram_rom_adr(21) <= ((cfg_bank2(21) AND $OpTx$FX_DC$173)
OR (cfg_bank(21) AND NOT $OpTx$FX_DC$173)); |
ram_rom_adr(22) <= ((cfg_bank2(22) AND $OpTx$FX_DC$173)
OR (cfg_bank(22) AND NOT $OpTx$FX_DC$173)); |
ram_rom_adr(23) <= ((cfg_bank2(23) AND $OpTx$FX_DC$173)
OR (cfg_bank(23) AND NOT $OpTx$FX_DC$173)); |
ram_rom_adr(24) <= ((cfg_bank2(24) AND $OpTx$FX_DC$173)
OR (cfg_bank(24) AND NOT $OpTx$FX_DC$173)); |
ram_rom_adr(25) <= ((cfg_bank2(25) AND $OpTx$FX_DC$173)
OR (cfg_bank(25) AND NOT $OpTx$FX_DC$173)); |
ram_rom_adr(26) <= ((cfg_bank2(26) AND $OpTx$FX_DC$173)
OR (cfg_bank(26) AND NOT $OpTx$FX_DC$173)); |
ram_rom_data_I(0) <= data(0).PIN;
ram_rom_data(0) <= ram_rom_data_I(0) when ram_rom_data_OE(0) = '1' else 'Z'; ram_rom_data_OE(0) <= NOT rw; |
ram_rom_data_I(1) <= data(1).PIN;
ram_rom_data(1) <= ram_rom_data_I(1) when ram_rom_data_OE(1) = '1' else 'Z'; ram_rom_data_OE(1) <= NOT rw; |
ram_rom_data_I(2) <= data(2).PIN;
ram_rom_data(2) <= ram_rom_data_I(2) when ram_rom_data_OE(2) = '1' else 'Z'; ram_rom_data_OE(2) <= NOT rw; |
ram_rom_data_I(3) <= data(3).PIN;
ram_rom_data(3) <= ram_rom_data_I(3) when ram_rom_data_OE(3) = '1' else 'Z'; ram_rom_data_OE(3) <= NOT rw; |
ram_rom_data_I(4) <= data(4).PIN;
ram_rom_data(4) <= ram_rom_data_I(4) when ram_rom_data_OE(4) = '1' else 'Z'; ram_rom_data_OE(4) <= NOT rw; |
ram_rom_data_I(5) <= data(5).PIN;
ram_rom_data(5) <= ram_rom_data_I(5) when ram_rom_data_OE(5) = '1' else 'Z'; ram_rom_data_OE(5) <= NOT rw; |
ram_rom_data_I(6) <= data(6).PIN;
ram_rom_data(6) <= ram_rom_data_I(6) when ram_rom_data_OE(6) = '1' else 'Z'; ram_rom_data_OE(6) <= NOT rw; |
ram_rom_data_I(7) <= data(7).PIN;
ram_rom_data(7) <= ram_rom_data_I(7) when ram_rom_data_OE(7) = '1' else 'Z'; ram_rom_data_OE(7) <= NOT rw; |
ram_rom_oe <= NOT ((rw AND phi2)); |
ram_rom_we <= NOT ((NOT rw AND phi2short)); |
rd4 <= ((NOT cfg_mode(2) AND cfg_mode(5) AND cfg_enable AND
NOT $OpTx$FX_DC$149) OR (cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND cfg_enable) OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND cfg_enable) OR (cfg_mode(2) AND cfg_mode(5) AND sic_8xxx_enable AND cfg_enable AND $OpTx$FX_DC$149) OR (NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND cfg_enable2 AND $OpTx$FX_DC$149)); |
rd5 <= ((NOT cfg_mode(2) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND
cfg_mode(3) AND cfg_enable) OR (NOT cfg_mode(2) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND cfg_enable AND NOT $OpTx$FX_DC$149) OR (cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND sic_axxx_enable AND cfg_enable) OR (cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND use_cart_logic/oss_bank(0) AND cfg_enable) OR (cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND use_cart_logic/oss_bank(1) AND cfg_enable) OR (NOT cfg_mode(2) AND cfg_mode(5) AND cfg_enable) OR (cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND cfg_enable) OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND cfg_enable) OR (NOT cfg_mode(1) AND NOT cfg_mode(4) AND cfg_mode(3) AND cfg_enable)); |
FDCPE_reset_n_sync: FDCPE port map (reset_n_sync,reset_n_sync1,NOT phi2short,'0','0'); |
FDCPE_reset_n_sync1: FDCPE port map (reset_n_sync1,reset_n,NOT phi2short,'0','0'); |
rom_ce <= (($OpTx$FX_DC$277)
OR (cfg_bank2(22).EXP) OR (NOT rw AND cfg_mode(2) AND NOT source_ram_or0000/source_ram_or0000_D2) OR (NOT rw AND NOT cfg_mode(5) AND NOT source_ram_or0000/source_ram_or0000_D2) OR (NOT rw AND cfg_mode(4) AND NOT source_ram_or0000/source_ram_or0000_D2) OR (NOT rw AND cfg_mode(3) AND NOT source_ram_or0000/source_ram_or0000_D2) OR (NOT rw AND NOT $OpTx$FX_DC$149 AND NOT source_ram_or0000/source_ram_or0000_D2) OR (cfg_source_ram AND source_ram_or0000/source_ram_or0000_D2)); |
FDCPE_rom_reset: FDCPE port map (rom_reset,'1',NOT phi2short,'0','0',reset_n_sync); |
FDCPE_sic_8xxx_enable: FDCPE port map (sic_8xxx_enable,sic_8xxx_enable_D,NOT phi2short,'0','0');
sic_8xxx_enable_D <= ((sic_8xxx_enable AND reset_n_sync AND NOT $OpTx$FX_DC$207) OR (data(5).PIN AND reset_n_sync AND $OpTx$FX_DC$207)); |
FDCPE_sic_axxx_enable: FDCPE port map (sic_axxx_enable,sic_axxx_enable_D,NOT phi2short,'0','0');
sic_axxx_enable_D <= ((NOT sic_axxx_enable AND reset_n_sync AND NOT $OpTx$FX_DC$207) OR (data(6).PIN AND reset_n_sync AND $OpTx$FX_DC$207)); |
source_ram_or0000/source_ram_or0000_D2 <= ((NOT cfg_mode(2) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND
NOT $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$164) OR (cfg_mode(5) AND cfg_mode(4) AND NOT $OpTx$FX_DC$164) OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3)) OR (cfg_mode(2) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT $OpTx$FX_DC$164) OR (NOT cfg_mode(1) AND NOT cfg_mode(4) AND cfg_mode(3) AND NOT $OpTx$FX_DC$164) OR (NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND NOT $OpTx$FX_DC$164)); |
use_cart_logic/N117/use_cart_logic/N117_D2 <= ((rd4_OBUF.EXP)
OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND NOT s4 AND cfg_enable) OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_mode(3) AND cfg_enable AND NOT s5) OR (NOT cfg_mode(1) AND NOT cfg_mode(4) AND cfg_mode(3) AND cfg_enable AND NOT s5) OR (cfg_mode(2) AND cfg_mode(5) AND sic_axxx_enable AND cfg_enable AND NOT s5 AND $OpTx$FX_DC$149) OR (NOT cfg_mode(2) AND NOT cfg_mode(0) AND NOT cfg_mode(4) AND cfg_mode(3) AND cfg_enable AND NOT s5) OR (NOT cfg_mode(2) AND cfg_mode(5) AND s4 AND cfg_enable AND NOT s5) OR (NOT cfg_mode(2) AND cfg_mode(5) AND NOT s4 AND cfg_enable AND NOT $OpTx$FX_DC$149) OR (cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND NOT s4 AND cfg_enable) OR (cfg_mode(5) AND NOT cfg_mode(1) AND cfg_mode(4) AND cfg_enable AND NOT s5)); |
use_cart_logic/N230/use_cart_logic/N230_D2 <= ((adr(6) AND NOT cfg_mode(2) AND cfg_mode(1) AND
NOT cfg_mode(0) AND NOT adr(7) AND adr(5) AND adr(4)) OR (adr(6) AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND cfg_mode(0) AND adr(7) AND NOT adr(5) AND adr(4)) OR (adr(6) AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND NOT cfg_mode(0) AND adr(7) AND adr(5) AND NOT adr(4))); |
use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2 <= ((NOT reset_n_sync)
OR (NOT adr(2) AND adr(0) AND adr(1) AND $OpTx$FX_DC$185)); |
use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2 <= ((NOT reset_n_sync)
OR (adr(2) AND NOT adr(0) AND NOT adr(1) AND $OpTx$FX_DC$185)); |
use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2 <= ((NOT reset_n_sync)
OR (NOT adr(2) AND adr(0) AND NOT adr(1) AND $OpTx$FX_DC$185)); |
use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2 <= ((NOT reset_n_sync)
OR (adr(2) AND NOT adr(0) AND adr(1) AND $OpTx$FX_DC$185)); |
use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 <= ((NOT reset_n_sync)
OR (adr(2) AND adr(0) AND adr(1) AND $OpTx$FX_DC$185)); |
FDCPE_use_cart_logic/oss_bank0: FDCPE port map (use_cart_logic/oss_bank(0),use_cart_logic/oss_bank_D(0),NOT phi2short,'0','0');
use_cart_logic/oss_bank_D(0) <= ((use_cart_logic/oss_bank(0) AND reset_n_sync AND NOT $OpTx$FX_DC$229) OR (NOT cctl AND NOT adr(3) AND cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND reset_n_sync AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208)); |
FDCPE_use_cart_logic/oss_bank1: FDCPE port map (use_cart_logic/oss_bank(1),use_cart_logic/oss_bank_D(1),NOT phi2short,'0','0');
use_cart_logic/oss_bank_D(1) <= ((use_cart_logic/oss_bank(1) AND reset_n_sync AND NOT $OpTx$FX_DC$229) OR (NOT cctl AND adr(0) AND cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cfg_mode(3) AND reset_n_sync AND $OpTx$FX_DC$149 AND NOT $OpTx$FX_DC$208)); |
use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 <= ((NOT reset_n_sync)
OR (NOT rw AND NOT cctl AND NOT adr(6) AND adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT mod_en AND adr(7) AND NOT adr(1) AND adr(5) AND NOT adr(4))); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |