Signal Name | Total Pterms | Total Inputs | Function Block | Macrocell | Power Mode | Slew Rate | Pin Number | Pin Type | Pin Use | Reg Init State | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
data<4> | 8 | 24 | FB2 | MC5 | LOW | SLOW | 1 | I/O/GTS3 | I/O | ||||
$OpTx$FX_DC$229 | 1 | 7 | FB2 | MC6 | LOW | 2 | I/O/GTS4 | (b) | |||||
$OpTx$FX_DC$221 | 2 | 7 | FB2 | MC8 | LOW | 3 | I/O/GTS1 | I | |||||
N91/N91_D2 | 2 | 7 | FB2 | MC9 | LOW | 4 | I/O/GTS2 | I | |||||
data<5> | 8 | 24 | FB2 | MC11 | LOW | SLOW | 6 | I/O | I/O | ||||
source_ram_or0000/source_ram_or0000_D2 | 6 | 8 | FB2 | MC12 | LOW | 7 | I/O | (b) | |||||
data<2> | 9 | 25 | FB2 | MC14 | LOW | SLOW | 8 | I/O | I/O | ||||
data<1> | 9 | 26 | FB2 | MC15 | LOW | SLOW | 9 | I/O | I/O | ||||
data<3> | 9 | 25 | FB2 | MC17 | LOW | SLOW | 10 | I/O | I/O | ||||
data<0> | 11 | 28 | FB1 | MC2 | LOW | SLOW | 11 | I/O | I/O | ||||
data<7> | 5 | 17 | FB1 | MC3 | LOW | SLOW | 12 | I/O | I/O | ||||
data<6> | 5 | 22 | FB1 | MC5 | LOW | SLOW | 13 | I/O | I/O | ||||
use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2 | 2 | 5 | FB1 | MC6 | LOW | 14 | I/O | I | |||||
use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2 | 2 | 5 | FB1 | MC8 | LOW | 15 | I/O | I | |||||
eeprom_cs | 2 | 4 | FB1 | MC9 | LOW | SLOW | 16 | I/O | O | SET | |||
$OpTx$FX_DC$269 | 2 | 3 | FB1 | MC11 | LOW | 17 | I/O | I | |||||
eeprom_sck | 2 | 4 | FB1 | MC12 | LOW | SLOW | 18 | I/O | O | RESET | |||
$OpTx$FX_DC$211 | 5 | 12 | FB1 | MC14 | LOW | 19 | I/O | (b) | |||||
eeprom_si | 2 | 4 | FB1 | MC15 | LOW | SLOW | 20 | I/O | O | RESET | |||
ram_rom_adr<26> | 2 | 3 | FB3 | MC5 | LOW | SLOW | 24 | I/O | O | ||||
ram_rom_adr<0> | 1 | 1 | FB3 | MC6 | LOW | SLOW | 25 | I/O | O | ||||
cfg_bank2<24> | 2 | 4 | FB3 | MC8 | LOW | 27 | I/O/GCK3 | I | RESET | ||||
ram_rom_adr<17> | 4 | 9 | FB3 | MC9 | LOW | SLOW | 28 | I/O | O | ||||
ram_rom_adr<25> | 2 | 3 | FB3 | MC11 | LOW | SLOW | 29 | I/O | O | ||||
rom_reset | 1 | 1 | FB3 | MC12 | LOW | SLOW | 30 | I/O | O | RESET | |||
ram_rom_data<7> | 2 | 2 | FB3 | MC14 | LOW | SLOW | 32 | I/O | I/O | ||||
ram_rom_data<6> | 2 | 2 | FB3 | MC15 | LOW | SLOW | 33 | I/O | I/O | ||||
cfg_bank<19> | 17 | 21 | FB3 | MC17 | LOW | 34 | I/O | (b) | RESET | ||||
ram_rom_data<5> | 2 | 2 | FB5 | MC2 | LOW | SLOW | 35 | I/O | I/O | ||||
ram_rom_data<4> | 2 | 2 | FB5 | MC5 | LOW | SLOW | 36 | I/O | I/O | ||||
ram_rom_data<3> | 2 | 2 | FB5 | MC6 | LOW | SLOW | 37 | I/O | I/O | ||||
ram_rom_data<2> | 2 | 2 | FB5 | MC8 | LOW | SLOW | 39 | I/O | I/O | ||||
ram_rom_data<1> | 2 | 2 | FB5 | MC9 | LOW | SLOW | 40 | I/O | I/O | ||||
ram_rom_data<0> | 2 | 2 | FB5 | MC11 | LOW | SLOW | 41 | I/O | I/O | ||||
ram_rom_oe | 1 | 2 | FB5 | MC12 | LOW | SLOW | 42 | I/O | O | ||||
ram_rom_adr<1> | 1 | 1 | FB5 | MC14 | LOW | SLOW | 43 | I/O | O | ||||
cfg_bank2<22> | 2 | 4 | FB5 | MC15 | LOW | 46 | I/O | (b) | RESET | ||||
rom_ce | 9 | 11 | FB5 | MC17 | LOW | SLOW | 49 | I/O | O | ||||
ram_rom_we | 1 | 2 | FB7 | MC2 | LOW | SLOW | 50 | I/O | O | ||||
ram_rom_adr<2> | 1 | 1 | FB7 | MC5 | LOW | SLOW | 52 | I/O | O | ||||
ram_rom_adr<3> | 1 | 1 | FB7 | MC6 | LOW | SLOW | 53 | I/O | O | ||||
ram_rom_adr<4> | 1 | 1 | FB7 | MC8 | LOW | SLOW | 54 | I/O | O | ||||
ram_rom_adr<5> | 1 | 1 | FB7 | MC9 | LOW | SLOW | 55 | I/O | O | ||||
ram_rom_adr<6> | 1 | 1 | FB7 | MC11 | LOW | SLOW | 56 | I/O | O | ||||
ram_rom_adr<7> | 1 | 1 | FB7 | MC12 | LOW | SLOW | 58 | I/O | O | ||||
ram_rom_adr<8> | 1 | 1 | FB7 | MC14 | LOW | SLOW | 59 | I/O | O | ||||
ram_rom_adr<18> | 3 | 8 | FB7 | MC15 | LOW | SLOW | 60 | I/O | O | ||||
ram_rom_adr<19> | 3 | 9 | FB7 | MC17 | LOW | SLOW | 61 | I/O | O | ||||
ram_rom_adr<22> | 2 | 3 | FB8 | MC2 | LOW | SLOW | 63 | I/O | O | ||||
ram_rom_adr<21> | 2 | 3 | FB8 | MC5 | LOW | SLOW | 64 | I/O | O | ||||
ram_rom_adr<20> | 2 | 3 | FB8 | MC6 | LOW | SLOW | 65 | I/O | O | ||||
ram_rom_adr<9> | 1 | 1 | FB8 | MC8 | LOW | SLOW | 66 | I/O | O | ||||
ram_rom_adr<10> | 1 | 1 | FB8 | MC9 | LOW | SLOW | 67 | I/O | O | ||||
ram_rom_adr<11> | 1 | 1 | FB8 | MC11 | LOW | SLOW | 68 | I/O | O | ||||
ram_rom_adr<12> | 7 | 8 | FB8 | MC12 | LOW | SLOW | 70 | I/O | O | ||||
ram_rom_adr<13> | 12 | 13 | FB8 | MC14 | LOW | SLOW | 71 | I/O | O | ||||
ram_rom_adr<14> | 3 | 7 | FB8 | MC15 | LOW | SLOW | 72 | I/O | O | ||||
mod_en | 2 | 12 | FB8 | MC17 | LOW | SLOW | 73 | I/O | O | RESET | |||
ram_rom_adr<15> | 4 | 9 | FB6 | MC2 | LOW | SLOW | 74 | I/O | O | ||||
ram_rom_adr<16> | 4 | 8 | FB6 | MC5 | LOW | SLOW | 76 | I/O | O | ||||
ram_rom_adr<23> | 2 | 3 | FB6 | MC6 | LOW | SLOW | 77 | I/O | O | ||||
ram_rom_adr<24> | 2 | 3 | FB6 | MC8 | LOW | SLOW | 78 | I/O | O | ||||
rd5 | 9 | 11 | FB6 | MC9 | LOW | SLOW | 79 | I/O | O | ||||
cfg_mode<0> | 2 | 4 | FB6 | MC11 | LOW | 80 | I/O | (b) | SET | ||||
rd4 | 5 | 9 | FB6 | MC12 | LOW | SLOW | 81 | I/O | O | ||||
use_cart_logic/N117/use_cart_logic/N117_D2 | 14 | 15 | FB6 | MC14 | LOW | 82 | I/O | I | |||||
ram_ce | 3 | 10 | FB6 | MC15 | LOW | SLOW | 85 | I/O | O | ||||
cfg_mode<5> | 2 | 4 | FB4 | MC5 | LOW | 89 | I/O | I | RESET | ||||
cfg_mode<4> | 2 | 4 | FB4 | MC6 | LOW | 90 | I/O | I | RESET | ||||
cfg_mode<2> | 2 | 4 | FB4 | MC8 | LOW | 91 | I/O | I | RESET | ||||
cfg_mode<1> | 2 | 4 | FB4 | MC9 | LOW | 92 | I/O | I | RESET | ||||
cfg_bank2<19> | 2 | 4 | FB4 | MC11 | LOW | 93 | I/O | I | RESET | ||||
cfg_bank2<18> | 2 | 4 | FB4 | MC12 | LOW | 94 | I/O | I | RESET | ||||
cfg_bank2<16> | 2 | 4 | FB4 | MC14 | LOW | 95 | I/O | I | RESET | ||||
cfg_bank2<15> | 2 | 4 | FB4 | MC15 | LOW | 96 | I/O | I | RESET | ||||
cfg_bank2<13> | 2 | 4 | FB4 | MC17 | LOW | 97 | I/O | I | RESET | ||||
$OpTx$INV$144 | 11 | 12 | FB2 | MC2 | LOW | 99 | I/O/GSR | I | |||||
$OpTx$FX_DC$149 | 1 | 2 | FB1 | MC1 | LOW | (b) | (b) | ||||||
use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 | 2 | 5 | FB1 | MC4 | LOW | (b) | (b) | ||||||
use_cart_logic/cfg_bank_21__or0000/use_cart_logic/cfg_bank_21__or0000_D2 | 2 | 5 | FB1 | MC7 | LOW | (b) | (b) | ||||||
use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2 | 2 | 5 | FB1 | MC10 | LOW | (b) | (b) | ||||||
cfg_enable2 | 5 | 7 | FB1 | MC13 | LOW | (b) | (b) | T | RESET | ||||
cfg_bank<15> | 19 | 25 | FB1 | MC16 | LOW | (b) | (b) | D | RESET | ||||
$OpTx$FX_DC$208 | 1 | 5 | FB1 | MC18 | LOW | (b) | (b) | ||||||
use_cart_logic/N230/use_cart_logic/N230_D2 | 3 | 7 | FB2 | MC1 | LOW | (b) | (b) | ||||||
$OpTx$FX_DC$244 | 4 | 6 | FB2 | MC3 | LOW | (b) | (b) | ||||||
data_7_IOBUFE/data_7_IOBUFE_TRST | 4 | 18 | FB2 | MC4 | LOW | (b) | (b) | ||||||
data_or0000/data_or0000_D2 | 3 | 16 | FB2 | MC7 | LOW | (b) | (b) | ||||||
use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 | 2 | 12 | FB2 | MC10 | LOW | (b) | (b) | ||||||
$OpTx$FX_DC$207 | 1 | 10 | FB2 | MC13 | LOW | (b) | (b) | ||||||
$OpTx$FX_DC$185 | 1 | 8 | FB2 | MC18 | LOW | (b) | (b) | ||||||
cfg_bank2<26> | 2 | 4 | FB3 | MC1 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank<16> | 23 | 24 | FB3 | MC3 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank2<25> | 2 | 4 | FB3 | MC7 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank2<23> | 2 | 4 | FB3 | MC10 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank<20> | 11 | 21 | FB3 | MC13 | LOW | (b) | (b) | D | RESET | ||||
$OpTx$FX_DC$158 | 1 | 2 | FB3 | MC18 | LOW | (b) | (b) | ||||||
cfg_bank<13> | 26 | 23 | FB4 | MC1 | LOW | (b) | (b) | D | RESET | ||||
reset_n_sync | 1 | 1 | FB4 | MC4 | LOW | (b) | (b) | D | RESET | ||||
cfg_mode<3> | 2 | 4 | FB4 | MC7 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank2<20> | 2 | 4 | FB4 | MC10 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank2<17> | 2 | 4 | FB4 | MC13 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank2<14> | 2 | 4 | FB4 | MC16 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank<14> | 16 | 25 | FB5 | MC1 | LOW | (b) | (b) | D | RESET | ||||
$OpTx$FX_DC$241 | 1 | 2 | FB5 | MC3 | LOW | (b) | (b) | ||||||
cfg_write_enable2 | 2 | 4 | FB5 | MC4 | LOW | (b) | (b) | D | RESET | ||||
cfg_write_enable | 2 | 4 | FB5 | MC7 | LOW | (b) | (b) | D | RESET | ||||
cfg_source_ram2 | 2 | 4 | FB5 | MC10 | LOW | (b) | (b) | D | RESET | ||||
cfg_source_ram | 2 | 4 | FB5 | MC13 | LOW | (b) | (b) | D | RESET | ||||
$OpTx$FX_DC$209 | 1 | 2 | FB6 | MC3 | LOW | (b) | (b) | ||||||
$OpTx$FX_DC$164 | 1 | 2 | FB6 | MC4 | LOW | (b) | (b) | ||||||
use_cart_logic/oss_bank<1> | 2 | 11 | FB6 | MC7 | LOW | (b) | (b) | D | RESET | ||||
$OpTx$FX_DC$277 | 4 | 7 | FB6 | MC10 | LOW | (b) | (b) | ||||||
cfg_enable | 28 | 26 | FB6 | MC18 | LOW | (b) | (b) | D | SET | ||||
reset_n_sync1 | 1 | 1 | FB7 | MC1 | LOW | (b) | (b) | D | RESET | ||||
$OpTx$FX_DC$217 | 1 | 2 | FB7 | MC3 | LOW | (b) | (b) | ||||||
sic_axxx_enable | 2 | 4 | FB7 | MC4 | LOW | (b) | (b) | D | SET | ||||
sic_8xxx_enable | 2 | 4 | FB7 | MC7 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank<26> | 2 | 4 | FB7 | MC10 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank<25> | 2 | 4 | FB7 | MC13 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank2<21> | 2 | 4 | FB7 | MC16 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank<18> | 14 | 24 | FB7 | MC18 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank<17> | 17 | 23 | FB8 | MC1 | LOW | (b) | (b) | D | RESET | ||||
$OpTx$FX_DC$173 | 1 | 6 | FB8 | MC3 | LOW | (b) | (b) | ||||||
use_cart_logic/oss_bank<0> | 2 | 11 | FB8 | MC4 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank<24> | 2 | 4 | FB8 | MC7 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank<23> | 2 | 4 | FB8 | MC10 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank<22> | 2 | 4 | FB8 | MC13 | LOW | (b) | (b) | D | RESET | ||||
cfg_bank<21> | 2 | 4 | FB8 | MC16 | LOW | (b) | (b) | D | RESET |