FB1
FB2
FB3
FB4
FB5
FB6
FB7
FB8
Signal Name
Total Product Terms
Product Terms
Location
Power Mode
Pin Number
PinType
Pin Use
use_cart_logic/N230/use_cart_logic/N230_D2
3
1_1
1_2
1_3
MC1
LOW
(b)
(b)
$OpTx$INV$144
11
1_4
1_5
2_1
2_2
2_3
2_4
2_5
3_2
3_3
3_4
3_5
MC2
LOW
99
I/O/GSR
I
$OpTx$FX_DC$244
4
3_1
4_3
4_4
4_5
MC3
LOW
(b)
(b)
data_7_IOBUFE/data_7_IOBUFE_TRST
4
4_1
4_2
5_4
5_5
MC4
LOW
(b)
(b)
data<4>
8
5_1
5_2
5_3
6_1
6_2
6_3
6_4
6_5
MC5
LOW
1
I/O/GTS3
I/O
$OpTx$FX_DC$229
1
7_4
MC6
LOW
2
I/O/GTS4
(b)
data_or0000/data_or0000_D2
3
7_1
7_2
7_3
MC7
LOW
(b)
(b)
$OpTx$FX_DC$221
2
8_1
8_2
MC8
LOW
3
I/O/GTS1
I
N91/N91_D2
2
9_1
9_2
MC9
LOW
4
I/O/GTS2
I
use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2
2
10_1
9_3
MC10
LOW
(b)
(b)
data<5>
8
10_2
10_3
10_4
10_5
11_1
11_2
11_3
11_4
MC11
LOW
6
I/O
I/O
source_ram_or0000/source_ram_or0000_D2
6
11_5
12_1
12_2
12_3
12_4
12_5
MC12
LOW
7
I/O
(b)
$OpTx$FX_DC$207
1
13_1
MC13
LOW
(b)
(b)
data<2>
9
13_2
13_3
13_4
13_5
14_1
14_2
14_3
14_4
14_5
MC14
LOW
8
I/O
I/O
data<1>
9
15_1
15_2
15_3
15_4
15_5
16_1
16_2
16_3
16_4
MC15
LOW
9
I/O
I/O
(unused)
0
MC16
(b)
(b)
data<3>
9
17_1
17_2
17_3
17_4
17_5
18_2
18_3
18_4
18_5
MC17
LOW
10
I/O
I/O
$OpTx$FX_DC$185
1
18_1
MC18
LOW
(b)
(b)
Signals Used By Logic in Function Block
$OpTx$FX_DC$149
$OpTx$FX_DC$164
$OpTx$FX_DC$208
ram_rom_data<5>.PIN
ram_rom_data<4>.PIN
ram_rom_data<3>.PIN
ram_rom_data<2>.PIN
ram_rom_data<1>.PIN
adr<0>
adr<1>
adr<2>
adr<3>
adr<4>
adr<5>
adr<6>
adr<7>
cctl
cfg_bank2<14>
cfg_bank2<15>
cfg_bank2<16>
cfg_bank2<17>
cfg_bank2<18>
cfg_bank2<22>
cfg_bank2<23>
cfg_bank2<24>
cfg_bank2<25>
cfg_bank2<26>
cfg_bank<14>
cfg_bank<15>
cfg_bank<16>
cfg_bank<17>
cfg_bank<18>
cfg_bank<22>
cfg_bank<23>
cfg_bank<24>
cfg_bank<25>
cfg_bank<26>
cfg_mode<0>
cfg_mode<1>
cfg_mode<2>
cfg_mode<3>
cfg_mode<4>
cfg_mode<5>
cfg_source_ram
cfg_source_ram2
cfg_write_enable2
data_7_IOBUFE/data_7_IOBUFE_TRST
data_or0000/data_or0000_D2
mod_en
phi2
reset_n_sync
rw
sic_8xxx_enable
use_cart_logic/N117/use_cart_logic/N117_D2