    cpldfit:  version P.20131013                        Xilinx Inc.
                                      Fitter Report
    Design Name: TheCart                             Date:  3-22-2026,  2:43PM
    Device Used: XC95144XL-10-TQ100
    Fitting Status: Successful

    *************************  Mapped Resource Summary  **************************

    Macrocells     Product Terms    Function Block   Registers      Pins
    Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot
    129/144 ( 90%) 492 /720  ( 68%) 367/432 ( 85%)   51 /144 ( 35%) 75 /81  ( 93%)

    ** Function Block Resources **

    Function    Mcells      FB Inps     Pterms      IO
    Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot
    FB1          15/18       49/54       44/90      10/11
    FB2          16/18       54/54*      86/90       8/10
    FB3          13/18       50/54       77/90       9/10
    FB4          18/18*      37/54       38/90      10/10*
    FB5          18/18*      29/54       35/90       9/10
    FB6          14/18       53/54       83/90       9/10
    FB7          17/18       42/54       64/90      10/10*
    FB8          18/18*      53/54       65/90      10/10*
                 -----       -----       -----      -----
                129/144     367/432     492/720     75/81

    * - Resource is exhausted

    ** Global Control Resources **

    Signal 'phi2short' mapped onto global clock net GCK2.
    Global output enable net(s) unused.
    Global set/reset net(s) unused.

    ** Pin Resources **

    Signal Type    Required     Mapped  |  Pin Type            Used    Total
    ------------------------------------|------------------------------------
    Input         :   20          20    |  I/O              :    68      73
    Output        :   38          38    |  GCK/IO           :     3       3
    Bidirectional :   16          16    |  GTS/IO           :     3       4
    GCK           :    1           1    |  GSR/IO           :     1       1
    GTS           :    0           0    |
    GSR           :    0           0    |
                     ----        ----
            Total     75          75

    ** Power Data **

    There are 0 macrocells in high performance mode (MCHP).
    There are 129 macrocells in low power mode (MCLP).
    End of Mapped Resource Summary
    **************************  Errors and Warnings  ***************************

    WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
       use the default filename of 'TheCart.ise'.
    INFO:Cpld - Inferring BUFG constraint for signal 'cctl' based upon the LOC
       constraint 'P27'. It is recommended that you declare this BUFG explicitedly
       in your design. Note that for certain device families the output of a BUFG
       constraint can not drive a gated clock, and the BUFG constraint will be
       ignored.
    INFO:Cpld - Inferring BUFG constraint for signal 'phi2' based upon the LOC
       constraint 'P22'. It is recommended that you declare this BUFG explicitedly
       in your design. Note that for certain device families the output of a BUFG
       constraint can not drive a gated clock, and the BUFG constraint will be
       ignored.
    WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'phi2_IBUF' is
       ignored. Most likely the signal is gated and therefore cannot be used as a
       global control signal.
    WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'cctl_IBUF' is
       ignored. Most likely the signal is gated and therefore cannot be used as a
       global control signal.
    *************************  Summary of Mapped Logic  ************************

    ** 54 Outputs **

    Signal                                                                            Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
    Name                                                                              Pts   Inps          No.  Type    Use     Mode Rate State
    data<0>                                                                           11    20    FB1_2   11   I/O     I/O     LOW  SLOW
    data<7>                                                                           6     16    FB1_3   12   I/O     I/O     LOW  SLOW
    data<6>                                                                           6     16    FB1_5   13   I/O     I/O     LOW  SLOW
    eeprom_cs                                                                         2     4     FB1_9   16   I/O     O       LOW  SLOW SET
    eeprom_sck                                                                        2     4     FB1_12  18   I/O     O       LOW  SLOW RESET
    eeprom_si                                                                         2     4     FB1_15  20   I/O     O       LOW  SLOW RESET
    data<4>                                                                           8     17    FB2_5   1    GTS/I/O I/O     LOW  SLOW
    data<5>                                                                           9     19    FB2_11  6    I/O     I/O     LOW  SLOW
    data<2>                                                                           9     18    FB2_14  8    I/O     I/O     LOW  SLOW
    data<1>                                                                           9     18    FB2_15  9    I/O     I/O     LOW  SLOW
    data<3>                                                                           9     18    FB2_17  10   I/O     I/O     LOW  SLOW
    ram_rom_adr<26>                                                                   2     3     FB3_5   24   I/O     O       LOW  SLOW
    ram_rom_adr<0>                                                                    1     1     FB3_6   25   I/O     O       LOW  SLOW
    ram_rom_adr<17>                                                                   4     9     FB3_9   28   I/O     O       LOW  SLOW
    ram_rom_adr<25>                                                                   2     3     FB3_11  29   I/O     O       LOW  SLOW
    rom_reset                                                                         1     1     FB3_12  30   I/O     O       LOW  SLOW RESET
    ram_rom_data<7>                                                                   2     2     FB3_14  32   I/O     I/O     LOW  SLOW
    ram_rom_data<6>                                                                   2     2     FB3_15  33   I/O     I/O     LOW  SLOW
    ram_rom_data<5>                                                                   2     2     FB5_2   35   I/O     I/O     LOW  SLOW
    ram_rom_data<4>                                                                   2     2     FB5_5   36   I/O     I/O     LOW  SLOW
    ram_rom_data<3>                                                                   2     2     FB5_6   37   I/O     I/O     LOW  SLOW
    ram_rom_data<2>                                                                   2     2     FB5_8   39   I/O     I/O     LOW  SLOW
    ram_rom_data<1>                                                                   2     2     FB5_9   40   I/O     I/O     LOW  SLOW
    ram_rom_data<0>                                                                   2     2     FB5_11  41   I/O     I/O     LOW  SLOW
    ram_rom_oe                                                                        1     2     FB5_12  42   I/O     O       LOW  SLOW
    ram_rom_adr<1>                                                                    1     1     FB5_14  43   I/O     O       LOW  SLOW
    rom_ce                                                                            3     5     FB5_17  49   I/O     O       LOW  SLOW
    ram_rom_adr<15>                                                                   3     7     FB6_2   74   I/O     O       LOW  SLOW
    ram_rom_adr<16>                                                                   4     8     FB6_5   76   I/O     O       LOW  SLOW
    ram_rom_adr<23>                                                                   2     3     FB6_6   77   I/O     O       LOW  SLOW
    ram_rom_adr<24>                                                                   2     3     FB6_8   78   I/O     O       LOW  SLOW
    rd5                                                                               5     8     FB6_9   79   I/O     O       LOW  SLOW
    rd4                                                                               6     9     FB6_12  81   I/O     O       LOW  SLOW
    ram_ce                                                                            2     5     FB6_15  85   I/O     O       LOW  SLOW
    ram_rom_we                                                                        1     2     FB7_2   50   I/O     O       LOW  SLOW
    ram_rom_adr<2>                                                                    1     1     FB7_5   52   I/O     O       LOW  SLOW
    ram_rom_adr<3>                                                                    1     1     FB7_6   53   I/O     O       LOW  SLOW
    ram_rom_adr<4>                                                                    1     1     FB7_8   54   I/O     O       LOW  SLOW
    ram_rom_adr<5>                                                                    1     1     FB7_9   55   I/O     O       LOW  SLOW
    ram_rom_adr<6>                                                                    1     1     FB7_11  56   I/O     O       LOW  SLOW

    Signal                                                                            Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
    Name                                                                              Pts   Inps          No.  Type    Use     Mode Rate State
    ram_rom_adr<7>                                                                    1     1     FB7_12  58   I/O     O       LOW  SLOW
    ram_rom_adr<8>                                                                    1     1     FB7_14  59   I/O     O       LOW  SLOW
    ram_rom_adr<18>                                                                   3     8     FB7_15  60   I/O     O       LOW  SLOW
    ram_rom_adr<19>                                                                   3     9     FB7_17  61   I/O     O       LOW  SLOW
    ram_rom_adr<22>                                                                   2     3     FB8_2   63   I/O     O       LOW  SLOW
    ram_rom_adr<21>                                                                   2     3     FB8_5   64   I/O     O       LOW  SLOW
    ram_rom_adr<20>                                                                   2     3     FB8_6   65   I/O     O       LOW  SLOW
    ram_rom_adr<9>                                                                    1     1     FB8_8   66   I/O     O       LOW  SLOW
    ram_rom_adr<10>                                                                   1     1     FB8_9   67   I/O     O       LOW  SLOW
    ram_rom_adr<11>                                                                   1     1     FB8_11  68   I/O     O       LOW  SLOW
    ram_rom_adr<12>                                                                   3     4     FB8_12  70   I/O     O       LOW  SLOW
    ram_rom_adr<13>                                                                   9     14    FB8_14  71   I/O     O       LOW  SLOW
    ram_rom_adr<14>                                                                   3     6     FB8_15  72   I/O     O       LOW  SLOW
    mod_en                                                                            2     9     FB8_17  73   I/O     O       LOW  SLOW RESET

    ** 75 Buried Nodes **

    Signal                                                                            Total Total Loc     Pwr  Reg Init
    Name                                                                              Pts   Inps          Mode State
    reset_n_sync1                                                                     1     1     FB1_1   LOW  RESET
    reset_n_sync                                                                      1     1     FB1_8   LOW  RESET
    $OpTx$FX_DC$444                                                                   1     2     FB1_10  LOW
    use_cart_logic/oss_bank<0>                                                        2     4     FB1_11  LOW  RESET
    oss_bank<1>                                                                       2     4     FB1_13  LOW  RESET
    data_7_IOBUFE/data_7_IOBUFE_TRST                                                  2     4     FB1_14  LOW
    cfg_mode<5>                                                                       2     4     FB1_16  LOW  RESET
    cfg_mode<2>                                                                       2     4     FB1_17  LOW  RESET
    cfg_mode<1>                                                                       2     4     FB1_18  LOW  RESET
    use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2                                2     8     FB2_1   LOW
    N219/N219_D2                                                                      13    12    FB2_2   LOW
    use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2  2     12    FB2_3   LOW
    use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2            2     9     FB2_4   LOW
    use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2  2     8     FB2_6   LOW
    data_or0000/data_or0000_D2                                                        3     15    FB2_7   LOW
    N41/N41_D2                                                                        3     8     FB2_8   LOW
    $OpTx$FX_DC$490                                                                   4     8     FB2_9   LOW
    N140/N140_D2                                                                      5     8     FB2_10  LOW
    $OpTx$FX_DC$504                                                                   5     8     FB2_12  LOW
    N247/N247_D2                                                                      1     8     FB2_18  LOW
    cfg_bank<13>                                                                      21    23    FB3_2   LOW  RESET
    cfg_bank<16>                                                                      20    23    FB3_8   LOW  RESET
    use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2          2     8     FB3_10  LOW
    use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2        2     8     FB3_13  LOW
    cfg_bank<21>                                                                      5     9     FB3_16  LOW  RESET
    cfg_bank<20>                                                                      13    22    FB3_18  LOW  RESET
    cfg_write_enable2                                                                 2     4     FB4_1   LOW  RESET
    cfg_write_enable                                                                  2     4     FB4_2   LOW  RESET
    cfg_source_ram2                                                                   2     4     FB4_3   LOW  RESET
    cfg_source_ram                                                                    2     4     FB4_4   LOW  RESET
    cfg_mode<0>                                                                       2     4     FB4_5   LOW  SET
    cfg_bank<26>                                                                      2     4     FB4_6   LOW  RESET
    cfg_bank<25>                                                                      2     4     FB4_7   LOW  RESET
    cfg_bank<24>                                                                      2     4     FB4_8   LOW  RESET
    cfg_bank<23>                                                                      2     4     FB4_9   LOW  RESET
    cfg_bank<22>                                                                      2     4     FB4_10  LOW  RESET
    cfg_bank2<26>                                                                     2     4     FB4_11  LOW  RESET
    cfg_bank2<25>                                                                     2     4     FB4_12  LOW  RESET
    cfg_bank2<24>                                                                     2     4     FB4_13  LOW  RESET
    cfg_bank2<15>                                                                     2     4     FB4_14  LOW  RESET

    Signal                                                                            Total Total Loc     Pwr  Reg Init
    Name                                                                              Pts   Inps          Mode State
    cfg_bank2<14>                                                                     2     4     FB4_15  LOW  RESET
    cfg_bank2<13>                                                                     2     4     FB4_16  LOW  RESET
    do_access_mux0002/do_access_mux0002_D2                                            3     7     FB4_17  LOW
    $OpTx$INV$433                                                                     3     5     FB4_18  LOW
    sic_axxx_enable                                                                   2     4     FB5_1   LOW  SET
    sic_8xxx_enable                                                                   2     4     FB5_3   LOW  RESET
    cfg_bank2<23>                                                                     2     4     FB5_4   LOW  RESET
    cfg_bank2<22>                                                                     2     4     FB5_7   LOW  RESET
    cfg_bank2<20>                                                                     2     4     FB5_10  LOW  RESET
    cfg_bank2<19>                                                                     2     4     FB5_13  LOW  RESET
    cfg_bank2<18>                                                                     2     4     FB5_15  LOW  RESET
    cfg_bank2<17>                                                                     2     4     FB5_16  LOW  RESET
    cfg_bank2<16>                                                                     2     4     FB5_18  LOW  RESET
    $OpTx$FX_DC$483                                                                   1     3     FB6_3   LOW
    $OpTx$FX_DC$457                                                                   1     3     FB6_4   LOW
    $OpTx$INV$431                                                                     6     13    FB6_7   LOW
    cfg_bank<15>                                                                      17    24    FB6_10  LOW  RESET
    $OpTx$FX_DC$451                                                                   1     3     FB6_13  LOW
    use_cart_logic/N252/use_cart_logic/N252_D2                                        3     7     FB6_14  LOW
    cfg_enable                                                                        30    26    FB6_18  LOW  SET
    cfg_bank<17>                                                                      16    23    FB7_1   LOW  RESET
    cctl_access_and0000/cctl_access_and0000_D2                                        1     5     FB7_3   LOW
    cfg_mode<4>                                                                       2     4     FB7_4   LOW  RESET
    cfg_mode<3>                                                                       2     4     FB7_7   LOW  RESET
    cfg_bank<19>                                                                      13    24    FB7_10  LOW  RESET
    cfg_bank<18>                                                                      13    24    FB7_13  LOW  RESET
    use_cart_logic/N69/use_cart_logic/N69_D2                                          3     6     FB7_16  LOW
    cfg_bank<14>                                                                      14    27    FB8_1   LOW  RESET
    use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2            2     8     FB8_3   LOW
    use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2        2     8     FB8_4   LOW
    cfg_bank2<21>                                                                     2     4     FB8_7   LOW  RESET
    cfg_enable2                                                                       5     10    FB8_10  LOW  RESET
    use_cart_logic/N11/use_cart_logic/N11_D2                                          6     7     FB8_13  LOW
    use_cart_logic/N23/use_cart_logic/N23_D2                                          7     8     FB8_16  LOW
    use_cart_logic/N16/use_cart_logic/N16_D2                                          1     5     FB8_18  LOW

    ** 21 Inputs **

    Signal                                                                            Loc     Pin  Pin     Pin
    Name                                                                                      No.  Type    Use
    adr<11>                                                                           FB1_6   14   I/O     I
    adr<10>                                                                           FB1_8   15   I/O     I
    eeprom_so                                                                         FB1_11  17   I/O     I
    phi2                                                                              FB1_17  22   GCK/I/O I
    rw                                                                                FB2_2   99   GSR/I/O I
    s4                                                                                FB2_8   3    GTS/I/O I
    s5                                                                                FB2_9   4    GTS/I/O I
    phi2short                                                                         FB3_2   23   GCK/I/O GCK/I
    cctl                                                                              FB3_8   27   GCK/I/O I
    adr<4>                                                                            FB4_2   87   I/O     I
    adr<2>                                                                            FB4_5   89   I/O     I
    adr<5>                                                                            FB4_6   90   I/O     I
    adr<1>                                                                            FB4_8   91   I/O     I
    adr<6>                                                                            FB4_9   92   I/O     I
    adr<0>                                                                            FB4_11  93   I/O     I
    adr<7>                                                                            FB4_12  94   I/O     I
    adr<8>                                                                            FB4_14  95   I/O     I
    adr<9>                                                                            FB4_15  96   I/O     I
    adr<12>                                                                           FB4_17  97   I/O     I
    reset_n                                                                           FB6_14  82   I/O     I
    adr<3>                                                                            FB6_17  86   I/O     I

    Legend:
    Pin No. - ~ - User Assigned
    **************************  Function Block Details  ************************
    Legend:
    Total Pt     - Total product terms used by the macrocell signal
    Imp Pt       - Product terms imported from other macrocells
    Exp Pt       - Product terms exported to other macrocells
                   in direction shown
    Unused Pt    - Unused local product terms remaining in macrocell
    Loc          - Location where logic was mapped in device
    Pin Type/Use - I  - Input             GCK - Global Clock
                   O  - Output            GTS - Global Output Enable
                  (b) - Buried macrocell  GSR - Global Set/Reset
    X            - Signal used as input to the macrocell logic.
    Pin No.      - ~  - User Assigned
    *********************************** FB1  ***********************************
    Number of function block inputs used/remaining:               49/5
    Number of signals used by logic mapping into function block:  49
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    reset_n_sync1         1       1<- \/5   0     FB1_1         (b)     (b)
    data<0>              11       6<-   0   0     FB1_2   11    I/O     I/O
    data<7>               6       2<- /\1   0     FB1_3   12    I/O     I/O
    (unused)              0       0   /\2   3     FB1_4         (b)     (b)
    data<6>               6       1<-   0   0     FB1_5   13    I/O     I/O
    (unused)              0       0   /\1   4     FB1_6   14    I/O     I
    (unused)              0       0     0   5     FB1_7         (b)
    reset_n_sync          1       0     0   4     FB1_8   15    I/O     I
    eeprom_cs             2       0     0   3     FB1_9   16    I/O     O
    $OpTx$FX_DC$444       1       0     0   4     FB1_10        (b)     (b)
    use_cart_logic/oss_bank<0>
                          2       0     0   3     FB1_11  17    I/O     I
    eeprom_sck            2       0     0   3     FB1_12  18    I/O     O
    oss_bank<1>           2       0     0   3     FB1_13        (b)     (b)
    data_7_IOBUFE/data_7_IOBUFE_TRST
                          2       0     0   3     FB1_14  19    I/O     (b)
    eeprom_si             2       0     0   3     FB1_15  20    I/O     O
    cfg_mode<5>           2       0     0   3     FB1_16        (b)     (b)
    cfg_mode<2>           2       0     0   3     FB1_17  22    GCK/I/O I
    cfg_mode<1>           2       0   \/1   2     FB1_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: N247/N247_D2                                18: cfg_bank<20>                            34: oss_bank<1>
      2: ram_rom_data<7>.PIN                         19: cfg_bank<21>                            35: phi2
      3: ram_rom_data<6>.PIN                         20: cfg_enable                              36: data<0>.PIN
      4: ram_rom_data<0>.PIN                         21: cfg_enable2                             37: data<1>.PIN
      5: adr<0>                                      22: cfg_mode<0>                             38: data<2>.PIN
      6: adr<1>                                      23: cfg_mode<1>                             39: data<5>.PIN
      7: adr<2>                                      24: cfg_mode<2>                             40: data<7>.PIN
      8: adr<3>                                      25: cfg_mode<5>                             41: reset_n
      9: cctl                                        26: cfg_write_enable                        42: reset_n_sync
     10: cctl_access_and0000/cctl_access_and0000_D2  27: data_7_IOBUFE/data_7_IOBUFE_TRST        43: reset_n_sync1
     11: cfg_bank2<13>                               28: data_or0000/data_or0000_D2              44: rw
     12: cfg_bank2<19>                               29: do_access_mux0002/do_access_mux0002_D2  45: sic_axxx_enable
     13: cfg_bank2<20>                               30: eeprom_cs                               46: use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2
     14: cfg_bank2<21>                               31: eeprom_sck                              47: use_cart_logic/oss_bank<0>
     15: cfg_bank<13>                                32: eeprom_si                               48: use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2
     16: cfg_bank<14>                                33: eeprom_so                               49: use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2
     17: cfg_bank<19>

    Signal                        1         2         3         4         5 FB
    Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
    reset_n_sync1        ........................................X......... 1
    data<0>              X..XXXXXXXX..XXX..XXXX...XXX...............X...... 20
    data<7>              XX..XXXXXX..X....XX..X....XX....X..........X...... 16
    data<6>              X.X.XXXXXX.X....XX...X....XX...............XX..... 16
    reset_n_sync         ..........................................X....... 1
    eeprom_cs            .............................X......X....X......X. 4
    $OpTx$FX_DC$444      ......................XX.......................... 2
    use_cart_logic/oss_bank<0>
                         .......X.................................X....XX.. 4
    eeprom_sck           ..............................X....X.....X......X. 4
    oss_bank<1>          ....X............................X.......X.....X.. 4
    data_7_IOBUFE/data_7_IOBUFE_TRST
                         ...........................XX.....X........X...... 4
    eeprom_si            ...............................X.......X.X......X. 4
    cfg_mode<5>          ........................X.............X..X...X.... 4
    cfg_mode<2>          .......................X.............X...X...X.... 4
    cfg_mode<1>          ......................X.............X....X...X.... 4
                        0----+----1----+----2----+----3----+----4----+----5
                                  0         0         0         0         0
    *********************************** FB2  ***********************************
    Number of function block inputs used/remaining:               54/0
    Number of signals used by logic mapping into function block:  54
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2
                          2       0   \/3   0     FB2_1         (b)     (b)
    N219/N219_D2         13       8<-   0   0     FB2_2   99    GSR/I/O I
    use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2
                          2       2<- /\5   0     FB2_3         (b)     (b)
    use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2
                          2       0   /\2   1     FB2_4         (b)     (b)
    data<4>               8       3<-   0   0     FB2_5   1     GTS/I/O I/O
    use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2
                          2       0   /\3   0     FB2_6   2     GTS/I/O (b)
    data_or0000/data_or0000_D2
                          3       0   \/1   1     FB2_7         (b)     (b)
    N41/N41_D2            3       1<- \/3   0     FB2_8   3     GTS/I/O I
    $OpTx$FX_DC$490       4       3<- \/4   0     FB2_9   4     GTS/I/O I
    N140/N140_D2          5       4<- \/4   0     FB2_10        (b)     (b)
    data<5>               9       4<-   0   0     FB2_11  6     I/O     I/O
    $OpTx$FX_DC$504       5       0     0   0     FB2_12  7     I/O     (b)
    (unused)              0       0   \/4   1     FB2_13        (b)     (b)
    data<2>               9       4<-   0   0     FB2_14  8     I/O     I/O
    data<1>               9       4<-   0   0     FB2_15  9     I/O     I/O
    (unused)              0       0   /\4   1     FB2_16        (b)     (b)
    data<3>               9       4<-   0   0     FB2_17  10    I/O     I/O
    N247/N247_D2          1       0   /\4   0     FB2_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: N247/N247_D2                                19: cfg_bank2<15>     37: cfg_bank<25>
      2: ram_rom_data<5>.PIN                         20: cfg_bank2<16>     38: cfg_bank<26>
      3: ram_rom_data<4>.PIN                         21: cfg_bank2<17>     39: cfg_mode<0>
      4: ram_rom_data<3>.PIN                         22: cfg_bank2<18>     40: cfg_mode<1>
      5: ram_rom_data<2>.PIN                         23: cfg_bank2<22>     41: cfg_mode<2>
      6: ram_rom_data<1>.PIN                         24: cfg_bank2<23>     42: cfg_mode<3>
      7: N41/N41_D2                                  25: cfg_bank2<24>     43: cfg_mode<4>
      8: adr<0>                                      26: cfg_bank2<25>     44: cfg_mode<5>
      9: adr<1>                                      27: cfg_bank2<26>     45: cfg_source_ram
     10: adr<2>                                      28: cfg_bank<14>      46: cfg_source_ram2
     11: adr<3>                                      29: cfg_bank<15>      47: cfg_write_enable2
     12: adr<4>                                      30: cfg_bank<16>      48: data_7_IOBUFE/data_7_IOBUFE_TRST
     13: adr<5>                                      31: cfg_bank<17>      49: data_or0000/data_or0000_D2
     14: adr<6>                                      32: cfg_bank<18>      50: reset_n_sync
     15: adr<7>                                      33: cfg_bank<19>      51: rw
     16: cctl                                        34: cfg_bank<22>      52: sic_8xxx_enable
     17: cctl_access_and0000/cctl_access_and0000_D2  35: cfg_bank<23>      53: use_cart_logic/N252/use_cart_logic/N252_D2
     18: cfg_bank2<14>                               36: cfg_bank<24>      54: use_cart_logic/N69/use_cart_logic/N69_D2

    Signal                        1         2         3         4         5         6 FB
    Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
    use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2
                         .......XXXX....XX................................XX......... 8
    N219/N219_D2         ...........XXXX.......................XXXXXX........XX...... 12
    use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2
                         ............XXXX......................XXXXXX.....XX......... 12
    use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2
                         ...............XX.....................XXXXXX.....X.......... 9
    data<4>              X.X....XXXX....XX...X....X....XX....X.....X....XX.X......... 17
    use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2
                         .......XXXX....XX................................XX......... 8
    data_or0000/data_or0000_D2
                         .......XXXX.XXXXX......................XXXXX......X......... 15
    N41/N41_D2           .......XXXX....XX.......................X.........X......... 8
    $OpTx$FX_DC$490      X...............X......................XXXXX......X......... 8
    N140/N140_D2         ......X........XX.....................X..XXX......X......... 8
    data<5>              XX.....XXXX....XX....X....X....XX....XX....X...XX.XX........ 19
    $OpTx$FX_DC$504      ..............X.X.....................XXXXXX................ 8
    data<2>              X...X..XXXX....XX.X....X....XX....X.....X.....XXX.X......... 18
    data<1>              X....X.XXXX....XXX....X....XX....X.....X....X..XX.X......... 18
    data<3>              X..X...XXXX....XX..X....X....XX....X.....X...X.XX.X......... 18
    N247/N247_D2         ............XXX........................XXXXX................ 8
                        0----+----1----+----2----+----3----+----4----+----5----+----6
                                  0         0         0         0         0         0
    *********************************** FB3  ***********************************
    Number of function block inputs used/remaining:               50/4
    Number of signals used by logic mapping into function block:  50
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    (unused)              0       0   \/5   0     FB3_1         (b)     (b)
    cfg_bank<13>         21      16<-   0   0     FB3_2   23    GCK/I/O GCK/I
    (unused)              0       0   /\5   0     FB3_3         (b)     (b)
    (unused)              0       0   /\5   0     FB3_4         (b)     (b)
    ram_rom_adr<26>       2       0   \/1   2     FB3_5   24    I/O     O
    ram_rom_adr<0>        1       1<- \/5   0     FB3_6   25    I/O     O
    (unused)              0       0   \/5   0     FB3_7         (b)     (b)
    cfg_bank<16>         20      15<-   0   0     FB3_8   27    GCK/I/O I
    ram_rom_adr<17>       4       4<- /\5   0     FB3_9   28    I/O     O
    use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2
                          2       1<- /\4   0     FB3_10        (b)     (b)
    ram_rom_adr<25>       2       0   /\1   2     FB3_11  29    I/O     O
    rom_reset             1       0     0   4     FB3_12  30    I/O     O
    use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2
                          2       0     0   3     FB3_13        (b)     (b)
    ram_rom_data<7>       2       0   \/1   2     FB3_14  32    I/O     I/O
    ram_rom_data<6>       2       1<- \/4   0     FB3_15  33    I/O     I/O
    cfg_bank<21>          5       4<- \/4   0     FB3_16        (b)     (b)
    (unused)              0       0   \/5   0     FB3_17  34    I/O     (b)
    cfg_bank<20>         13       9<- \/1   0     FB3_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: $OpTx$FX_DC$444                             18: cfg_bank2<25>     35: data<3>.PIN
      2: $OpTx$FX_DC$457                             19: cfg_bank2<26>     36: data<6>.PIN
      3: $OpTx$FX_DC$490                             20: cfg_bank<13>      37: data<7>.PIN
      4: N140/N140_D2                                21: cfg_bank<16>      38: reset_n_sync
      5: N247/N247_D2                                22: cfg_bank<17>      39: rw
      6: N41/N41_D2                                  23: cfg_bank<20>      40: s5
      7: adr<0>                                      24: cfg_bank<21>      41: use_cart_logic/N16/use_cart_logic/N16_D2
      8: adr<1>                                      25: cfg_bank<25>      42: use_cart_logic/N23/use_cart_logic/N23_D2
      9: adr<2>                                      26: cfg_bank<26>      43: use_cart_logic/N252/use_cart_logic/N252_D2
     10: adr<3>                                      27: cfg_mode<0>       44: use_cart_logic/N69/use_cart_logic/N69_D2
     11: adr<4>                                      28: cfg_mode<1>       45: use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2
     12: adr<5>                                      29: cfg_mode<2>       46: use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2
     13: adr<6>                                      30: cfg_mode<3>       47: use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2
     14: adr<7>                                      31: cfg_mode<4>       48: use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2
     15: cctl                                        32: cfg_mode<5>       49: use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2
     16: cctl_access_and0000/cctl_access_and0000_D2  33: data<0>.PIN       50: use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2
     17: cfg_bank2<17>                               34: data<2>.PIN

    Signal                        1         2         3         4         5         6 FB
    Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
    cfg_bank<13>         XX.X..X...XXXXXX...X......XXXXXXX....XX...XX.....X.......... 23
    ram_rom_adr<26>      ..................X......X..............X................... 3
    ram_rom_adr<0>       ......X..................................................... 1
    cfg_bank<16>         .XX.XX.XXX...XXX....X.....XXXXXX.XX...X......X.XX........... 23
    ram_rom_adr<17>      ................X....X....XXX.X........XXX.................. 9
    use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2
                         ......X.XX....XX.....................XX.....X............... 8
    ram_rom_adr<25>      .................X......X...............X................... 3
    rom_reset            .....................................X...................... 1
    use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2
                         ......X.XX....XX.....................XX.......X............. 8
    ram_rom_data<7>      ....................................X.X..................... 2
    ram_rom_data<6>      ...................................X..X..................... 2
    cfg_bank<21>         ....XX.................X..X.....X...X.......XX..X........... 9
    cfg_bank<20>         ....XX.XXX..XXXX......X...XXXXXX...XX.X......X.XX........... 22
                        0----+----1----+----2----+----3----+----4----+----5----+----6
                                  0         0         0         0         0         0
    *********************************** FB4  ***********************************
    Number of function block inputs used/remaining:               37/17
    Number of signals used by logic mapping into function block:  37
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    cfg_write_enable2     2       0     0   3     FB4_1         (b)     (b)
    cfg_write_enable      2       0     0   3     FB4_2   87    I/O     I
    cfg_source_ram2       2       0     0   3     FB4_3         (b)     (b)
    cfg_source_ram        2       0     0   3     FB4_4         (b)     (b)
    cfg_mode<0>           2       0     0   3     FB4_5   89    I/O     I
    cfg_bank<26>          2       0     0   3     FB4_6   90    I/O     I
    cfg_bank<25>          2       0     0   3     FB4_7         (b)     (b)
    cfg_bank<24>          2       0     0   3     FB4_8   91    I/O     I
    cfg_bank<23>          2       0     0   3     FB4_9   92    I/O     I
    cfg_bank<22>          2       0     0   3     FB4_10        (b)     (b)
    cfg_bank2<26>         2       0     0   3     FB4_11  93    I/O     I
    cfg_bank2<25>         2       0     0   3     FB4_12  94    I/O     I
    cfg_bank2<24>         2       0     0   3     FB4_13        (b)     (b)
    cfg_bank2<15>         2       0     0   3     FB4_14  95    I/O     I
    cfg_bank2<14>         2       0     0   3     FB4_15  96    I/O     I
    cfg_bank2<13>         2       0     0   3     FB4_16        (b)     (b)
    do_access_mux0002/do_access_mux0002_D2
                          3       0     0   2     FB4_17  97    I/O     I
    $OpTx$INV$433         3       0     0   2     FB4_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: $OpTx$INV$433     14: cfg_source_ram     26: reset_n_sync
      2: cfg_bank2<13>     15: cfg_source_ram2    27: rw
      3: cfg_bank2<14>     16: cfg_write_enable   28: s4
      4: cfg_bank2<15>     17: cfg_write_enable2  29: s5
      5: cfg_bank2<24>     18: data<0>.PIN        30: use_cart_logic/N11/use_cart_logic/N11_D2
      6: cfg_bank2<25>     19: data<1>.PIN        31: use_cart_logic/N16/use_cart_logic/N16_D2
      7: cfg_bank2<26>     20: data<2>.PIN        32: use_cart_logic/N23/use_cart_logic/N23_D2
      8: cfg_bank<22>      21: data<3>.PIN        33: use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2
      9: cfg_bank<23>      22: data<4>.PIN        34: use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2
     10: cfg_bank<24>      23: data<5>.PIN        35: use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2
     11: cfg_bank<25>      24: rd4                36: use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2
     12: cfg_bank<26>      25: rd5                37: use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2
     13: cfg_mode<0>

    Signal                        1         2         3         4 FB
    Name                0----+----0----+----0----+----0----+----0 Inputs
    cfg_write_enable2    ................X..X.....X..........X... 4
    cfg_write_enable     ...............X.X.......X..........X... 4
    cfg_source_ram2      ..............X.....X....X..........X... 4
    cfg_source_ram       .............X....X......X..........X... 4
    cfg_mode<0>          ............X....X.......X.........X.... 4
    cfg_bank<26>         ...........X..........X..X........X..... 4
    cfg_bank<25>         ..........X..........X...X........X..... 4
    cfg_bank<24>         .........X..........X....X........X..... 4
    cfg_bank<23>         ........X..........X.....X........X..... 4
    cfg_bank<22>         .......X..........X......X........X..... 4
    cfg_bank2<26>        ......X...............X..X.......X...... 4
    cfg_bank2<25>        .....X...............X...X.......X...... 4
    cfg_bank2<24>        ....X...............X....X.......X...... 4
    cfg_bank2<15>        ...X...............X.....X......X....... 4
    cfg_bank2<14>        ..X...............X......X......X....... 4
    cfg_bank2<13>        .X...............X.......X......X....... 4
    do_access_mux0002/do_access_mux0002_D2
                         X......................XX..XXX.X........ 7
    $OpTx$INV$433        ...............XX.........X...XX........ 5
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    *********************************** FB5  ***********************************
    Number of function block inputs used/remaining:               29/25
    Number of signals used by logic mapping into function block:  29
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    sic_axxx_enable       2       0     0   3     FB5_1         (b)     (b)
    ram_rom_data<5>       2       0     0   3     FB5_2   35    I/O     I/O
    sic_8xxx_enable       2       0     0   3     FB5_3         (b)     (b)
    cfg_bank2<23>         2       0     0   3     FB5_4         (b)     (b)
    ram_rom_data<4>       2       0     0   3     FB5_5   36    I/O     I/O
    ram_rom_data<3>       2       0     0   3     FB5_6   37    I/O     I/O
    cfg_bank2<22>         2       0     0   3     FB5_7         (b)     (b)
    ram_rom_data<2>       2       0     0   3     FB5_8   39    I/O     I/O
    ram_rom_data<1>       2       0     0   3     FB5_9   40    I/O     I/O
    cfg_bank2<20>         2       0     0   3     FB5_10        (b)     (b)
    ram_rom_data<0>       2       0     0   3     FB5_11  41    I/O     I/O
    ram_rom_oe            1       0     0   4     FB5_12  42    I/O     O
    cfg_bank2<19>         2       0     0   3     FB5_13        (b)     (b)
    ram_rom_adr<1>        1       0     0   4     FB5_14  43    I/O     O
    cfg_bank2<18>         2       0     0   3     FB5_15  46    I/O     (b)
    cfg_bank2<17>         2       0     0   3     FB5_16        (b)     (b)
    rom_ce                3       0     0   2     FB5_17  49    I/O     O
    cfg_bank2<16>         2       0     0   3     FB5_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: adr<1>            11: do_access_mux0002/do_access_mux0002_D2  21: reset_n_sync
      2: cfg_bank2<16>     12: phi2                                    22: rw
      3: cfg_bank2<17>     13: data<0>.PIN                             23: sic_8xxx_enable
      4: cfg_bank2<18>     14: data<1>.PIN                             24: sic_axxx_enable
      5: cfg_bank2<19>     15: data<2>.PIN                             25: use_cart_logic/N16/use_cart_logic/N16_D2
      6: cfg_bank2<20>     16: data<3>.PIN                             26: use_cart_logic/N23/use_cart_logic/N23_D2
      7: cfg_bank2<22>     17: data<4>.PIN                             27: use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2
      8: cfg_bank2<23>     18: data<5>.PIN                             28: use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2
      9: cfg_source_ram    19: data<6>.PIN                             29: use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2
     10: cfg_source_ram2   20: data<7>.PIN

    Signal                        1         2         3         4 FB
    Name                0----+----0----+----0----+----0----+----0 Inputs
    sic_axxx_enable      ..................X.X..X....X........... 4
    ram_rom_data<5>      .................X...X.................. 2
    sic_8xxx_enable      .................X..X.X.....X........... 4
    cfg_bank2<23>        .......X......X.....X......X............ 4
    ram_rom_data<4>      ................X....X.................. 2
    ram_rom_data<3>      ...............X.....X.................. 2
    cfg_bank2<22>        ......X......X......X......X............ 4
    ram_rom_data<2>      ..............X......X.................. 2
    ram_rom_data<1>      .............X.......X.................. 2
    cfg_bank2<20>        .....X.............XX.....X............. 4
    ram_rom_data<0>      ............X........X.................. 2
    ram_rom_oe           ...........X.........X.................. 2
    cfg_bank2<19>        ....X.............X.X.....X............. 4
    ram_rom_adr<1>       X....................................... 1
    cfg_bank2<18>        ...X.............X..X.....X............. 4
    cfg_bank2<17>        ..X.............X...X.....X............. 4
    rom_ce               ........XXX.............XX.............. 5
    cfg_bank2<16>        .X.............X....X.....X............. 4
                        0----+----1----+----2----+----3----+----4
                                  0         0         0         0
    *********************************** FB6  ***********************************
    Number of function block inputs used/remaining:               53/1
    Number of signals used by logic mapping into function block:  53
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    (unused)              0       0   /\5   0     FB6_1         (b)     (b)
    ram_rom_adr<15>       3       3<- /\5   0     FB6_2   74    I/O     O
    $OpTx$FX_DC$483       1       0   /\3   1     FB6_3         (b)     (b)
    $OpTx$FX_DC$457       1       0     0   4     FB6_4         (b)     (b)
    ram_rom_adr<16>       4       0     0   1     FB6_5   76    I/O     O
    ram_rom_adr<23>       2       0   \/2   1     FB6_6   77    I/O     O
    $OpTx$INV$431         6       2<- \/1   0     FB6_7         (b)     (b)
    ram_rom_adr<24>       2       1<- \/4   0     FB6_8   78    I/O     O
    rd5                   5       4<- \/4   0     FB6_9   79    I/O     O
    cfg_bank<15>         17      12<-   0   0     FB6_10        (b)     (b)
    (unused)              0       0   /\5   0     FB6_11  80    I/O     (b)
    rd4                   6       4<- /\3   0     FB6_12  81    I/O     O
    $OpTx$FX_DC$451       1       0   /\4   0     FB6_13        (b)     (b)
    use_cart_logic/N252/use_cart_logic/N252_D2
                          3       0   \/2   0     FB6_14  82    I/O     I
    ram_ce                2       2<- \/5   0     FB6_15  85    I/O     O
    (unused)              0       0   \/5   0     FB6_16        (b)     (b)
    (unused)              0       0   \/5   0     FB6_17  86    I/O     I
    cfg_enable           30      25<-   0   0     FB6_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: $OpTx$FX_DC$451                             19: cfg_bank2<24>                           37: data<2>.PIN
      2: $OpTx$INV$431                               20: cfg_bank<15>                            38: data<3>.PIN
      3: N140/N140_D2                                21: cfg_bank<16>                            39: data<4>.PIN
      4: N219/N219_D2                                22: cfg_bank<23>                            40: data<5>.PIN
      5: N247/N247_D2                                23: cfg_bank<24>                            41: data<6>.PIN
      6: adr<0>                                      24: cfg_enable                              42: data<7>.PIN
      7: adr<1>                                      25: cfg_enable2                             43: rw
      8: adr<2>                                      26: cfg_mode<0>                             44: s5
      9: adr<3>                                      27: cfg_mode<1>                             45: sic_8xxx_enable
     10: adr<4>                                      28: cfg_mode<2>                             46: sic_axxx_enable
     11: adr<5>                                      29: cfg_mode<3>                             47: use_cart_logic/N11/use_cart_logic/N11_D2
     12: adr<6>                                      30: cfg_mode<4>                             48: use_cart_logic/N16/use_cart_logic/N16_D2
     13: adr<7>                                      31: cfg_mode<5>                             49: use_cart_logic/N23/use_cart_logic/N23_D2
     14: cctl                                        32: cfg_source_ram                          50: use_cart_logic/N252/use_cart_logic/N252_D2
     15: cctl_access_and0000/cctl_access_and0000_D2  33: cfg_source_ram2                         51: use_cart_logic/N69/use_cart_logic/N69_D2
     16: cfg_bank2<15>                               34: do_access_mux0002/do_access_mux0002_D2  52: use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2
     17: cfg_bank2<16>                               35: data<0>.PIN                             53: use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2
     18: cfg_bank2<23>                               36: data<1>.PIN

    Signal                        1         2         3         4         5         6 FB
    Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
    ram_rom_adr<15>      X..............X...X.........X.............X...XX........... 7
    $OpTx$FX_DC$483      ...........................XX.................X............. 3
    $OpTx$FX_DC$457      .........XXX................................................ 3
    ram_rom_adr<16>      ................X...X.....XX.X.............X...XX........... 8
    ram_rom_adr<23>      .................X...X.........................X............ 3
    $OpTx$INV$431        ........XX..................X.X...XXXXXXXXX................. 13
    ram_rom_adr<24>      ..................X...X........................X............ 3
    rd5                  .......................X.XXX.XX..............XX............. 8
    cfg_bank<15>         ..XXX.XXXX..XXX....X.....XXXXXX....XX.....X......XXXX....... 24
    rd4                  .......................XXXXXXXX.............X............... 9
    $OpTx$FX_DC$451      .........................XXX................................ 3
    use_cart_logic/N252/use_cart_logic/N252_D2
                         .........XXXX............XXX................................ 7
    ram_ce               ...............................XXX.............XX........... 5
    cfg_enable           .X.XXXXXXXXXXXX........X.XXXXXX...X......XX......XXX........ 26
                        0----+----1----+----2----+----3----+----4----+----5----+----6
                                  0         0         0         0         0         0
    *********************************** FB7  ***********************************
    Number of function block inputs used/remaining:               42/12
    Number of signals used by logic mapping into function block:  42
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    cfg_bank<17>         16      11<-   0   0     FB7_1         (b)     (b)
    ram_rom_we            1       0   /\4   0     FB7_2   50    I/O     O
    cctl_access_and0000/cctl_access_and0000_D2
                          1       0     0   4     FB7_3         (b)     (b)
    cfg_mode<4>           2       0     0   3     FB7_4         (b)     (b)
    ram_rom_adr<2>        1       0     0   4     FB7_5   52    I/O     O
    ram_rom_adr<3>        1       0     0   4     FB7_6   53    I/O     O
    cfg_mode<3>           2       0     0   3     FB7_7         (b)     (b)
    ram_rom_adr<4>        1       0     0   4     FB7_8   54    I/O     O
    ram_rom_adr<5>        1       0   \/4   0     FB7_9   55    I/O     O
    cfg_bank<19>         13       8<-   0   0     FB7_10        (b)     (b)
    ram_rom_adr<6>        1       0   /\4   0     FB7_11  56    I/O     O
    ram_rom_adr<7>        1       0   \/4   0     FB7_12  58    I/O     O
    cfg_bank<18>         13       8<-   0   0     FB7_13        (b)     (b)
    ram_rom_adr<8>        1       0   /\4   0     FB7_14  59    I/O     O
    ram_rom_adr<18>       3       0     0   2     FB7_15  60    I/O     O
    use_cart_logic/N69/use_cart_logic/N69_D2
                          3       0     0   2     FB7_16        (b)     (b)
    ram_rom_adr<19>       3       0   \/2   0     FB7_17  61    I/O     O
    (unused)              0       0   \/5   0     FB7_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: $OpTx$FX_DC$457   15: cctl                                        29: phi2short
      2: $OpTx$FX_DC$490   16: cctl_access_and0000/cctl_access_and0000_D2  30: data<3>.PIN
      3: $OpTx$FX_DC$504   17: cfg_bank2<18>                               31: data<4>.PIN
      4: N247/N247_D2      18: cfg_bank2<19>                               32: data<5>.PIN
      5: N41/N41_D2        19: cfg_bank<17>                                33: data<6>.PIN
      6: adr<0>            20: cfg_bank<18>                                34: reset_n_sync
      7: adr<1>            21: cfg_bank<19>                                35: rw
      8: adr<2>            22: cfg_mode<0>                                 36: s5
      9: adr<3>            23: cfg_mode<1>                                 37: use_cart_logic/N16/use_cart_logic/N16_D2
     10: adr<4>            24: cfg_mode<2>                                 38: use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2
     11: adr<5>            25: cfg_mode<3>                                 39: use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2
     12: adr<6>            26: cfg_mode<4>                                 40: use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2
     13: adr<7>            27: cfg_mode<5>                                 41: use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2
     14: adr<8>            28: mod_en                                      42: use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2

    Signal                        1         2         3         4         5 FB
    Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
    cfg_bank<17>         .X.XX.XXXX..X.XX..X..XXXXXX..XX...X..X.XX......... 23
    ram_rom_we           ............................X.....X............... 2
    cctl_access_and0000/cctl_access_and0000_D2
                         .........XXXX..............X...................... 5
    cfg_mode<4>          .........................X....X..X....X........... 4
    ram_rom_adr<2>       .......X.......................................... 1
    ram_rom_adr<3>       ........X......................................... 1
    cfg_mode<3>          ........................X....X...X....X........... 4
    ram_rom_adr<4>       .........X........................................ 1
    ram_rom_adr<5>       ..........X....................................... 1
    cfg_bank<19>         ..XXXXXX..XXX.XX....XXXXXXX....XX.X....XXX........ 24
    ram_rom_adr<6>       ...........X...................................... 1
    ram_rom_adr<7>       ............X..................................... 1
    cfg_bank<18>         ..XXX.XXXXX.X.XX...X.XXXXXX...XX..X..X.XX......... 24
    ram_rom_adr<8>       .............X.................................... 1
    ram_rom_adr<18>      ................X..X..XX.XX........XX............. 8
    use_cart_logic/N69/use_cart_logic/N69_D2
                         X...........X........XXXX......................... 6
    ram_rom_adr<19>      .................X..XXXX.XX........XX............. 9
                        0----+----1----+----2----+----3----+----4----+----5
                                  0         0         0         0         0
    *********************************** FB8  ***********************************
    Number of function block inputs used/remaining:               53/1
    Number of signals used by logic mapping into function block:  53
    Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
    Name                Pt      Pt    Pt  Pt               #    Type    Use
    cfg_bank<14>         14       9<-   0   0     FB8_1         (b)     (b)
    ram_rom_adr<22>       2       2<- /\5   0     FB8_2   63    I/O     O
    use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2
                          2       0   /\2   1     FB8_3         (b)     (b)
    use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2
                          2       0     0   3     FB8_4         (b)     (b)
    ram_rom_adr<21>       2       0     0   3     FB8_5   64    I/O     O
    ram_rom_adr<20>       2       0     0   3     FB8_6   65    I/O     O
    cfg_bank2<21>         2       0     0   3     FB8_7         (b)     (b)
    ram_rom_adr<9>        1       0     0   4     FB8_8   66    I/O     O
    ram_rom_adr<10>       1       0     0   4     FB8_9   67    I/O     O
    cfg_enable2           5       0     0   0     FB8_10        (b)     (b)
    ram_rom_adr<11>       1       0     0   4     FB8_11  68    I/O     O
    ram_rom_adr<12>       3       0   \/2   0     FB8_12  70    I/O     O
    use_cart_logic/N11/use_cart_logic/N11_D2
                          6       2<- \/1   0     FB8_13        (b)     (b)
    ram_rom_adr<13>       9       4<-   0   0     FB8_14  71    I/O     O
    ram_rom_adr<14>       3       1<- /\3   0     FB8_15  72    I/O     O
    use_cart_logic/N23/use_cart_logic/N23_D2
                          7       3<- /\1   0     FB8_16        (b)     (b)
    mod_en                2       0   /\3   0     FB8_17  73    I/O     O
    use_cart_logic/N16/use_cart_logic/N16_D2
                          1       0   \/4   0     FB8_18        (b)     (b)

    Signals Used by Logic in Function Block
      1: $OpTx$FX_DC$444                             19: cfg_bank2<13>     37: oss_bank<1>
      2: $OpTx$FX_DC$451                             20: cfg_bank2<14>     38: data<0>.PIN
      3: $OpTx$FX_DC$483                             21: cfg_bank2<20>     39: data<1>.PIN
      4: N140/N140_D2                                22: cfg_bank2<21>     40: reset_n_sync
      5: N219/N219_D2                                23: cfg_bank2<22>     41: rw
      6: N247/N247_D2                                24: cfg_bank<13>      42: s4
      7: adr<0>                                      25: cfg_bank<14>      43: s5
      8: adr<10>                                     26: cfg_bank<20>      44: use_cart_logic/N11/use_cart_logic/N11_D2
      9: adr<11>                                     27: cfg_bank<21>      45: use_cart_logic/N16/use_cart_logic/N16_D2
     10: adr<12>                                     28: cfg_bank<22>      46: use_cart_logic/N23/use_cart_logic/N23_D2
     11: adr<1>                                      29: cfg_enable2       47: use_cart_logic/N252/use_cart_logic/N252_D2
     12: adr<2>                                      30: cfg_mode<0>       48: use_cart_logic/N69/use_cart_logic/N69_D2
     13: adr<3>                                      31: cfg_mode<1>       49: use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2
     14: adr<4>                                      32: cfg_mode<2>       50: use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2
     15: adr<7>                                      33: cfg_mode<3>       51: use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2
     16: adr<9>                                      34: cfg_mode<4>       52: use_cart_logic/oss_bank<0>
     17: cctl                                        35: cfg_mode<5>       53: use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2
     18: cctl_access_and0000/cctl_access_and0000_D2  36: mod_en

    Signal                        1         2         3         4         5         6 FB
    Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
    cfg_bank<14>         XX.XXXX...X.XXX.XX......X....XXXXXX..XX.X.....XXXX..X....... 27
    ram_rom_adr<22>      ......................X....X................X............... 3
    use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2
                         ..........XXX...XX.....................XX.........X......... 8
    use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2
                         ......X...X.X...XX.....................XX.........X......... 8
    ram_rom_adr<21>      .....................X....X.................X............... 3
    ram_rom_adr<20>      ....................X....X..................X............... 3
    cfg_bank2<21>        .....................X...............X.X........X........... 4
    ram_rom_adr<9>       ...............X............................................ 1
    ram_rom_adr<10>      .......X.................................................... 1
    cfg_enable2          ......X...XXX...XX..........X........X.XX................... 10
    ram_rom_adr<11>      ........X................................................... 1
    ram_rom_adr<12>      ..X......X.......................X.................X........ 4
    use_cart_logic/N11/use_cart_logic/N11_D2
                         .............................XXXX.X.X..............X........ 7
    ram_rom_adr<13>      ..X......X........X....X......XX.XX.X....XXXXX.............. 14
    ram_rom_adr<14>      ...................X....X........X........X.XX.............. 6
    use_cart_logic/N23/use_cart_logic/N23_D2
                         X............................XXXXXX.........X............... 8
    mod_en               ......X...XX....XX.................X...XX.........X......... 9
    use_cart_logic/N16/use_cart_logic/N16_D2
                         .X..............................XXX......X.................. 5
                        0----+----1----+----2----+----3----+----4----+----5----+----6
                                  0         0         0         0         0         0
    *******************************  Equations  ********************************

    ********** Mapped Logic **********

    $OpTx$FX_DC$444 <= (cfg_mode(2) AND cfg_mode(1));

    $OpTx$FX_DC$451 <= (NOT cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(1));

    $OpTx$FX_DC$457 <= (NOT adr(6) AND NOT adr(5) AND NOT adr(4));

    $OpTx$FX_DC$483 <= (cfg_mode(2) AND NOT cfg_mode(3) AND
    	use_cart_logic/N11/use_cart_logic/N11_D2);

    $OpTx$FX_DC$490 <= ((NOT cfg_mode(2) AND NOT cfg_mode(1) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2)
    	OR (NOT cfg_mode(5) AND cfg_mode(4) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2)
    	OR (cfg_mode(2) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT N247/N247_D2)
    	OR (rw AND cfg_mode(4)));

    $OpTx$FX_DC$504 <= ((NOT cfg_mode(0) AND NOT cfg_mode(5) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2)
    	OR (cfg_mode(2) AND NOT cfg_mode(5) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2)
    	OR (NOT cfg_mode(2) AND cfg_mode(3) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2)
    	OR (cfg_mode(4) AND cfg_mode(1) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2)
    	OR (NOT cfg_mode(3) AND NOT cfg_mode(4) AND adr(7) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2));

    $OpTx$INV$431 <= ((cfg_mode(5) AND cfg_mode(3) AND data(7).PIN)
    	OR (cfg_mode(5) AND data(7).PIN AND data(2).PIN AND
    	data(1).PIN AND data(0).PIN AND data(5).PIN AND data(4).PIN AND
    	data(3).PIN AND data(6).PIN)
    	OR (rw AND cfg_mode(5))
    	OR (adr(3) AND NOT cfg_mode(5))
    	OR (NOT cfg_mode(5) AND NOT cfg_mode(3))
    	OR (NOT cfg_mode(5) AND adr(4)));

    $OpTx$INV$433 <= ((rw)
    	OR (cfg_write_enable AND
    	use_cart_logic/N23/use_cart_logic/N23_D2)
    	OR (cfg_write_enable2 AND
    	use_cart_logic/N16/use_cart_logic/N16_D2));

    N140/N140_D2 <= ((NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cctl AND N41/N41_D2)
    	OR (NOT cfg_mode(3) AND NOT cfg_mode(4) AND NOT cctl AND N41/N41_D2)
    	OR (NOT rw AND cfg_mode(0) AND NOT cfg_mode(5) AND NOT cctl AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2)
    	OR (cfg_mode(0) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cctl AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2)
    	OR (NOT rw AND NOT cctl AND N41/N41_D2));

    N219/N219_D2 <= ((cfg_mode(2) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND
    	adr(5))
    	OR (NOT cfg_mode(5) AND NOT cfg_mode(3) AND adr(4) AND
    	NOT use_cart_logic/N69/use_cart_logic/N69_D2)
    	OR (NOT cfg_mode(5) AND cfg_mode(1) AND
    	NOT use_cart_logic/N252/use_cart_logic/N252_D2 AND NOT use_cart_logic/N69/use_cart_logic/N69_D2)
    	OR (cfg_mode(2) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND
    	adr(6))
    	OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT adr(6) AND
    	NOT use_cart_logic/N69/use_cart_logic/N69_D2)
    	OR (cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND
    	NOT cfg_mode(3) AND NOT cfg_mode(4))
    	OR (cfg_mode(0) AND NOT cfg_mode(5) AND cfg_mode(3) AND
    	NOT use_cart_logic/N252/use_cart_logic/N252_D2 AND NOT use_cart_logic/N69/use_cart_logic/N69_D2)
    	OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND
    	NOT adr(5) AND NOT use_cart_logic/N69/use_cart_logic/N69_D2)
    	OR (NOT cfg_mode(5) AND cfg_mode(4))
    	OR (cfg_mode(2) AND NOT cfg_mode(3) AND cfg_mode(1))
    	OR (cfg_mode(2) AND cfg_mode(4) AND cfg_mode(1))
    	OR (NOT cfg_mode(3) AND NOT cfg_mode(4) AND adr(7))
    	OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND
    	NOT adr(7)));

    N247/N247_D2 <= (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(3) AND
    	NOT cfg_mode(4) AND NOT cfg_mode(1) AND NOT adr(6) AND NOT adr(7) AND NOT adr(5));

    N41/N41_D2 <= ((NOT rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1))
    	OR (NOT rw AND NOT cctl AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2)
    	OR (NOT cfg_mode(2) AND NOT cctl AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2));

    cctl_access_and0000/cctl_access_and0000_D2 <= (NOT mod_en AND NOT adr(6) AND adr(7) AND adr(5) AND NOT adr(4));

    FDCPE_cfg_bank213: FDCPE port map (cfg_bank2(13),cfg_bank2_D(13),NOT phi2short,'0','0');
    cfg_bank2_D(13) <= ((cfg_bank2(13) AND
    	NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
    	OR (data(0).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));

    FDCPE_cfg_bank214: FDCPE port map (cfg_bank2(14),cfg_bank2_D(14),NOT phi2short,'0','0');
    cfg_bank2_D(14) <= ((cfg_bank2(14) AND
    	NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
    	OR (data(1).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));

    FDCPE_cfg_bank215: FDCPE port map (cfg_bank2(15),cfg_bank2_D(15),NOT phi2short,'0','0');
    cfg_bank2_D(15) <= ((cfg_bank2(15) AND
    	NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
    	OR (data(2).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));

    FDCPE_cfg_bank216: FDCPE port map (cfg_bank2(16),cfg_bank2_D(16),NOT phi2short,'0','0');
    cfg_bank2_D(16) <= ((cfg_bank2(16) AND
    	NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
    	OR (data(3).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));

    FDCPE_cfg_bank217: FDCPE port map (cfg_bank2(17),cfg_bank2_D(17),NOT phi2short,'0','0');
    cfg_bank2_D(17) <= ((cfg_bank2(17) AND
    	NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
    	OR (data(4).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));

    FDCPE_cfg_bank218: FDCPE port map (cfg_bank2(18),cfg_bank2_D(18),NOT phi2short,'0','0');
    cfg_bank2_D(18) <= ((cfg_bank2(18) AND
    	NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
    	OR (data(5).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));

    FDCPE_cfg_bank219: FDCPE port map (cfg_bank2(19),cfg_bank2_D(19),NOT phi2short,'0','0');
    cfg_bank2_D(19) <= ((cfg_bank2(19) AND
    	NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
    	OR (data(6).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));

    FDCPE_cfg_bank220: FDCPE port map (cfg_bank2(20),cfg_bank2_D(20),NOT phi2short,'0','0');
    cfg_bank2_D(20) <= ((cfg_bank2(20) AND
    	NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2)
    	OR (data(7).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));

    FDCPE_cfg_bank221: FDCPE port map (cfg_bank2(21),cfg_bank2_D(21),NOT phi2short,'0','0');
    cfg_bank2_D(21) <= ((cfg_bank2(21) AND
    	NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)
    	OR (data(0).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2));

    FDCPE_cfg_bank222: FDCPE port map (cfg_bank2(22),cfg_bank2_D(22),NOT phi2short,'0','0');
    cfg_bank2_D(22) <= ((cfg_bank2(22) AND
    	NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)
    	OR (data(1).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2));

    FDCPE_cfg_bank223: FDCPE port map (cfg_bank2(23),cfg_bank2_D(23),NOT phi2short,'0','0');
    cfg_bank2_D(23) <= ((cfg_bank2(23) AND
    	NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)
    	OR (data(2).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2));

    FDCPE_cfg_bank224: FDCPE port map (cfg_bank2(24),cfg_bank2_D(24),NOT phi2short,'0','0');
    cfg_bank2_D(24) <= ((cfg_bank2(24) AND
    	NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)
    	OR (data(3).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2));

    FDCPE_cfg_bank225: FDCPE port map (cfg_bank2(25),cfg_bank2_D(25),NOT phi2short,'0','0');
    cfg_bank2_D(25) <= ((cfg_bank2(25) AND
    	NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)
    	OR (data(4).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2));

    FDCPE_cfg_bank226: FDCPE port map (cfg_bank2(26),cfg_bank2_D(26),NOT phi2short,'0','0');
    cfg_bank2_D(26) <= ((cfg_bank2(26) AND
    	NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)
    	OR (data(5).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2));

    FDCPE_cfg_bank13: FDCPE port map (cfg_bank(13),cfg_bank_D(13),NOT phi2short,'0','0');
    cfg_bank_D(13) <= ((cfg_bank(20).EXP)
    	OR (cfg_mode(5) AND cfg_mode(4) AND data(0).PIN AND
    	NOT $OpTx$FX_DC$444 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND
    	N140/N140_D2)
    	OR (NOT cfg_mode(5) AND NOT cfg_mode(3) AND NOT cfg_mode(1) AND
    	cfg_bank(13) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (NOT cfg_mode(5) AND cfg_mode(1) AND adr(7) AND
    	cfg_bank(13) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(5) AND
    	adr(6) AND cfg_bank(13) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (cfg_mode(0) AND cfg_mode(3) AND NOT cfg_mode(4) AND
    	cfg_mode(1) AND cfg_bank(13) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (EXP20_.EXP)
    	OR (adr(0) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cctl AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND
    	use_cart_logic/N69/use_cart_logic/N69_D2)
    	OR (cfg_mode(0) AND NOT cfg_mode(5) AND adr(7) AND
    	cfg_bank(13) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND NOT use_cart_logic/N252/use_cart_logic/N252_D2)
    	OR (cfg_mode(0) AND NOT cfg_mode(5) AND adr(5) AND
    	cfg_bank(13) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND NOT use_cart_logic/N69/use_cart_logic/N69_D2)
    	OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(1) AND
    	cfg_bank(13) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND NOT use_cart_logic/N252/use_cart_logic/N252_D2)
    	OR (NOT cfg_mode(2) AND NOT cfg_mode(5) AND NOT adr(6) AND
    	cfg_bank(13) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND NOT use_cart_logic/N69/use_cart_logic/N69_D2)
    	OR (reset_n_sync AND cfg_bank(13) AND NOT N140/N140_D2)
    	OR (data(0).PIN AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND
    	N140/N140_D2)
    	OR (cfg_bank(13) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND $OpTx$FX_DC$444 AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_bank(13) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (NOT cfg_mode(5) AND cfg_mode(4) AND cfg_bank(13) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2));

    FDCPE_cfg_bank14: FDCPE port map (cfg_bank(14),cfg_bank_D(14),NOT phi2short,'0','0');
    cfg_bank_D(14) <= ((NOT rw AND cfg_mode(5) AND cfg_mode(4) AND NOT cctl AND
    	data(1).PIN AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT $OpTx$FX_DC$444 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT cfg_mode(5) AND cfg_mode(3) AND NOT cfg_mode(4) AND NOT cctl AND
    	NOT adr(1) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 AND use_cart_logic/N252/use_cart_logic/N252_D2)
    	OR (NOT rw AND cfg_mode(5) AND cfg_mode(3) AND NOT cfg_mode(4) AND
    	NOT cctl AND data(0).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT $OpTx$FX_DC$451 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT rw AND NOT cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(5) AND
    	NOT cfg_mode(4) AND NOT cfg_mode(1) AND NOT cctl AND data(1).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2)
    	OR (adr(0) AND NOT cfg_mode(0) AND NOT cfg_mode(2) AND
    	cfg_mode(5) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND
    	NOT adr(7) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT cfg_mode(5) AND adr(4) AND cfg_bank(14) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND $OpTx$FX_DC$451 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT cfg_mode(2) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND
    	NOT cfg_mode(1) AND cfg_bank(14) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cctl AND adr(1) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 AND use_cart_logic/N69/use_cart_logic/N69_D2)
    	OR (NOT rw AND NOT adr(3) AND NOT adr(0) AND NOT cctl AND data(1).PIN AND
    	NOT adr(1) AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2)
    	OR (cfg_bank(14) AND
    	NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 AND NOT N140/N140_D2)
    	OR (cfg_bank(14) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 AND N219/N219_D2)
    	OR (NOT rw AND NOT cctl AND data(0).PIN AND N247/N247_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (cfg_mode(2) AND NOT cfg_mode(5) AND NOT cfg_mode(3) AND
    	cfg_bank(14) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (cfg_mode(5) AND NOT cfg_mode(4) AND cfg_bank(14) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND $OpTx$FX_DC$451 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));

    FDCPE_cfg_bank15: FDCPE port map (cfg_bank(15),cfg_bank_D(15),NOT phi2short,'0','0');
    cfg_bank_D(15) <= ((adr(2) AND NOT cfg_mode(5) AND NOT cfg_mode(4) AND NOT cctl AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 AND use_cart_logic/N69/use_cart_logic/N69_D2)
    	OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(4) AND
    	NOT cfg_mode(1) AND cfg_bank(15) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND
    	adr(4) AND cfg_bank(15) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT rw AND NOT adr(3) AND NOT adr(2) AND NOT cctl AND data(2).PIN AND
    	NOT adr(1) AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (rd4_OBUF.EXP)
    	OR (NOT adr(2) AND NOT cfg_mode(5) AND cfg_mode(3) AND
    	NOT cfg_mode(4) AND NOT cctl AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 AND use_cart_logic/N252/use_cart_logic/N252_D2)
    	OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(3) AND
    	NOT cfg_mode(4) AND NOT cctl AND data(1).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND
    	NOT cfg_mode(1) AND NOT cctl AND data(2).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT rw AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND
    	cfg_mode(1) AND NOT cctl AND data(2).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT rw AND cfg_mode(5) AND cfg_mode(3) AND NOT cfg_mode(4) AND
    	cfg_mode(1) AND NOT cctl AND data(1).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (cfg_bank(15) AND
    	NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 AND NOT N140/N140_D2)
    	OR (cfg_bank(15) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 AND N219/N219_D2)
    	OR (NOT rw AND NOT cctl AND data(1).PIN AND N247/N247_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT cfg_mode(5) AND NOT cfg_mode(3) AND NOT cfg_mode(1) AND
    	cfg_bank(15) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND
    	NOT cfg_mode(1) AND cfg_bank(15) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));

    FDCPE_cfg_bank16: FDCPE port map (cfg_bank(16),cfg_bank_D(16),NOT phi2short,'0','0');
    cfg_bank_D(16) <= ((adr_0_IBUF$BUF0.EXP)
    	OR (cfg_mode(2) AND NOT cfg_mode(5) AND cfg_mode(1) AND
    	cfg_bank(16) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (cfg_mode(2) AND cfg_mode(4) AND cfg_mode(1) AND
    	cfg_bank(16) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT cfg_mode(3) AND NOT cfg_mode(4) AND adr(7) AND
    	cfg_bank(16) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(3) AND
    	NOT cfg_mode(4) AND cfg_bank(16) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT cfg_mode(0) AND NOT cfg_mode(5) AND NOT cfg_mode(3) AND
    	cfg_bank(16) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2 AND NOT $OpTx$FX_DC$457)
    	OR (NOT rw AND NOT adr(3) AND NOT adr(2) AND NOT cctl AND data(3).PIN AND
    	NOT adr(1) AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (cfg_mode(0) AND cfg_mode(5) AND NOT cfg_mode(3) AND
    	NOT cfg_mode(4) AND cfg_bank(16) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT N247/N247_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(3) AND
    	NOT cfg_mode(4) AND NOT cctl AND data(2).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND
    	NOT cfg_mode(1) AND NOT cctl AND data(3).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT rw AND NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND
    	cfg_mode(1) AND NOT cctl AND data(3).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (cfg_bank(16) AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2 AND $OpTx$FX_DC$490)
    	OR (cfg_bank(16) AND
    	NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 AND NOT N41/N41_D2)
    	OR (rw AND cfg_mode(0) AND cfg_mode(5) AND cfg_bank(16) AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT rw AND NOT cctl AND data(2).PIN AND N247/N247_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (cfg_mode(0) AND NOT cfg_mode(5) AND cfg_mode(3) AND
    	cfg_bank(16) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2));

    FDCPE_cfg_bank17: FDCPE port map (cfg_bank(17),cfg_bank_D(17),NOT phi2short,'0','0');
    cfg_bank_D(17) <= ((NOT rw AND NOT adr(3) AND NOT adr(2) AND NOT cctl AND data(4).PIN AND
    	NOT adr(1) AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(3) AND
    	NOT cfg_mode(4) AND NOT cctl AND data(3).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND
    	NOT cfg_mode(1) AND NOT cctl AND data(4).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT rw AND cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND
    	cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND data(4).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (cart_mem_adr(19).EXP)
    	OR (NOT cfg_mode(0) AND cfg_mode(4) AND cfg_mode(1) AND
    	cfg_bank(17) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (cfg_mode(2) AND cfg_mode(4) AND cfg_mode(1) AND
    	cfg_bank(17) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT cfg_mode(2) AND cfg_mode(3) AND NOT cfg_mode(4) AND
    	cfg_bank(17) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT cfg_mode(2) AND NOT cfg_mode(4) AND adr(7) AND
    	cfg_bank(17) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND
    	NOT cfg_mode(4) AND cfg_bank(17) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (cfg_bank(17) AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2 AND $OpTx$FX_DC$490)
    	OR (cfg_bank(17) AND
    	NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 AND NOT N41/N41_D2)
    	OR (NOT rw AND NOT cctl AND data(3).PIN AND N247/N247_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT cfg_mode(0) AND NOT cfg_mode(5) AND cfg_bank(17) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (cfg_mode(2) AND NOT cfg_mode(5) AND cfg_bank(17) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2));

    FDCPE_cfg_bank18: FDCPE port map (cfg_bank(18),cfg_bank_D(18),NOT phi2short,'0','0');
    cfg_bank_D(18) <= ((NOT cfg_mode(0) AND NOT cfg_mode(4) AND NOT cfg_mode(1) AND
    	cfg_bank(18) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT N247/N247_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (cfg_mode(2) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND
    	cfg_bank(18) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT N247/N247_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT rw AND NOT adr(3) AND NOT adr(2) AND NOT cctl AND data(5).PIN AND
    	NOT adr(1) AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND
    	NOT cfg_mode(1) AND NOT cctl AND data(5).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT rw AND cfg_mode(0) AND cfg_mode(2) AND cfg_mode(5) AND
    	cfg_mode(3) AND NOT cfg_mode(4) AND NOT cctl AND data(4).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(3) AND
    	NOT cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND data(4).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND
    	NOT cfg_mode(3) AND NOT cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND NOT adr(7) AND
    	adr(5) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND
    	NOT cfg_mode(3) AND NOT cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND NOT adr(7) AND
    	adr(4) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (cfg_bank(18) AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2 AND $OpTx$FX_DC$504)
    	OR (cfg_bank(18) AND
    	NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 AND NOT N41/N41_D2)
    	OR (NOT rw AND NOT cctl AND data(4).PIN AND N247/N247_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT cfg_mode(2) AND NOT cfg_mode(1) AND cfg_bank(18) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND
    	cfg_bank(18) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2));

    FDCPE_cfg_bank19: FDCPE port map (cfg_bank(19),cfg_bank_D(19),NOT phi2short,'0','0');
    cfg_bank_D(19) <= ((NOT cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(3) AND
    	cfg_bank(19) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (NOT cfg_mode(4) AND NOT cfg_mode(1) AND cfg_bank(19) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT N247/N247_D2 AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (cfg_mode(0) AND cfg_mode(5) AND NOT cfg_mode(3) AND
    	cfg_mode(1) AND cfg_bank(19) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (NOT rw AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
    	data(6).PIN AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (NOT rw AND cfg_mode(0) AND cfg_mode(2) AND cfg_mode(5) AND
    	cfg_mode(4) AND NOT cfg_mode(1) AND NOT cctl AND data(6).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (NOT rw AND cfg_mode(2) AND cfg_mode(5) AND cfg_mode(3) AND
    	NOT cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND data(5).PIN AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(5) AND
    	NOT cfg_mode(3) AND NOT cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND adr(6) AND
    	NOT adr(7) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND
    	NOT cfg_mode(3) AND NOT cfg_mode(4) AND cfg_mode(1) AND NOT cctl AND NOT adr(7) AND
    	adr(5) AND NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (cfg_bank(19) AND
    	NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 AND NOT N41/N41_D2)
    	OR (cfg_bank(19) AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 AND $OpTx$FX_DC$504)
    	OR (NOT rw AND NOT cctl AND data(5).PIN AND N247/N247_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (NOT cfg_mode(0) AND cfg_mode(4) AND cfg_bank(19) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (NOT cfg_mode(2) AND NOT cfg_mode(1) AND cfg_bank(19) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2));

    FDCPE_cfg_bank20: FDCPE port map (cfg_bank(20),cfg_bank_D(20),NOT phi2short,'0','0');
    cfg_bank_D(20) <= ((cfg_bank(21).EXP)
    	OR (NOT rw AND NOT cctl AND data(6).PIN AND N247/N247_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (cfg_mode(0) AND NOT cfg_mode(2) AND cfg_bank(20) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT cfg_mode(0) AND NOT cfg_mode(1) AND cfg_bank(20) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT cfg_mode(0) AND adr(7) AND cfg_bank(20) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT cfg_mode(1) AND cfg_bank(20) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT N247/N247_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (cfg_bank(20) AND
    	NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 AND NOT N41/N41_D2)
    	OR (NOT cfg_mode(5) AND cfg_bank(20) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (cfg_mode(4) AND cfg_bank(20) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (NOT cfg_mode(0) AND cfg_mode(3) AND cfg_bank(20) AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));

    FDCPE_cfg_bank21: FDCPE port map (cfg_bank(21),cfg_bank_D(21),NOT phi2short,'0','0');
    cfg_bank_D(21) <= ((NOT cfg_mode(0) AND cfg_bank(21) AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (cfg_bank(21) AND NOT N247/N247_D2 AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (cfg_bank(21) AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 AND NOT N41/N41_D2)
    	OR (data(7).PIN AND N247/N247_D2 AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2 AND N41/N41_D2)
    	OR (data(0).PIN AND
    	NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2 AND
    	use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));

    FDCPE_cfg_bank22: FDCPE port map (cfg_bank(22),cfg_bank_D(22),NOT phi2short,'0','0');
    cfg_bank_D(22) <= ((cfg_bank(22) AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (data(1).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));

    FDCPE_cfg_bank23: FDCPE port map (cfg_bank(23),cfg_bank_D(23),NOT phi2short,'0','0');
    cfg_bank_D(23) <= ((cfg_bank(23) AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (data(2).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));

    FDCPE_cfg_bank24: FDCPE port map (cfg_bank(24),cfg_bank_D(24),NOT phi2short,'0','0');
    cfg_bank_D(24) <= ((cfg_bank(24) AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (data(3).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));

    FDCPE_cfg_bank25: FDCPE port map (cfg_bank(25),cfg_bank_D(25),NOT phi2short,'0','0');
    cfg_bank_D(25) <= ((cfg_bank(25) AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (data(4).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));

    FDCPE_cfg_bank26: FDCPE port map (cfg_bank(26),cfg_bank_D(26),NOT phi2short,'0','0');
    cfg_bank_D(26) <= ((cfg_bank(26) AND
    	NOT use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (data(5).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2));

    FDCPE_cfg_enable: FDCPE port map (cfg_enable,cfg_enable_D,NOT phi2short,'0','0');
    cfg_enable_D <= ((
    	use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2)
    	OR (cart_mem_adr(15).EXP)
    	OR (NOT cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(3) AND
    	cfg_enable AND NOT cctl_access_and0000/cctl_access_and0000_D2)
    	OR (cfg_mode(2) AND NOT cfg_mode(3) AND cfg_enable AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT N247/N247_D2)
    	OR (NOT cfg_mode(5) AND cfg_mode(3) AND cfg_enable AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND N219/N219_D2)
    	OR (NOT cfg_mode(3) AND NOT cfg_mode(1) AND cfg_enable AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2 AND NOT N247/N247_D2)
    	OR (NOT rw AND NOT adr(3) AND NOT adr(2) AND NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2)
    	OR (EXP25_.EXP)
    	OR (adr(0) AND cfg_enable AND
    	cctl_access_and0000/cctl_access_and0000_D2)
    	OR (rw AND cfg_mode(0) AND cfg_mode(5) AND cfg_enable)
    	OR (rw AND cfg_mode(2) AND cfg_enable AND
    	NOT use_cart_logic/N69/use_cart_logic/N69_D2)
    	OR (rw AND cfg_mode(5) AND cfg_mode(3) AND cfg_enable)
    	OR (NOT cfg_mode(3) AND cfg_mode(4) AND cfg_enable AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2)
    	OR (cctl AND cfg_enable)
    	OR (rw AND cfg_enable AND
    	cctl_access_and0000/cctl_access_and0000_D2)
    	OR (adr(3) AND cfg_enable AND
    	cctl_access_and0000/cctl_access_and0000_D2)
    	OR (adr(2) AND cfg_enable AND
    	cctl_access_and0000/cctl_access_and0000_D2));

    FTCPE_cfg_enable2: FTCPE port map (cfg_enable2,cfg_enable2_T,NOT phi2short,'0','0');
    cfg_enable2_T <= ((cfg_enable2 AND NOT reset_n_sync)
    	OR (NOT rw AND NOT adr(3) AND adr(2) AND adr(0) AND cfg_enable2 AND
    	NOT cctl AND NOT data(0).PIN AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2)
    	OR (NOT rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT cfg_enable2 AND
    	NOT cctl AND NOT adr(1) AND reset_n_sync AND
    	cctl_access_and0000/cctl_access_and0000_D2)
    	OR (NOT rw AND NOT adr(3) AND adr(2) AND NOT cfg_enable2 AND NOT cctl AND
    	data(0).PIN AND NOT adr(1) AND reset_n_sync AND
    	cctl_access_and0000/cctl_access_and0000_D2)
    	OR (NOT rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT cfg_enable2 AND
    	NOT cctl AND adr(1) AND reset_n_sync AND
    	cctl_access_and0000/cctl_access_and0000_D2));

    FDCPE_cfg_mode0: FDCPE port map (cfg_mode(0),cfg_mode_D(0),NOT phi2short,'0','0');
    cfg_mode_D(0) <= ((NOT cfg_mode(0) AND
    	NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)
    	OR (NOT data(0).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2));

    FDCPE_cfg_mode1: FDCPE port map (cfg_mode(1),cfg_mode_D(1),NOT phi2short,'0','0');
    cfg_mode_D(1) <= ((cfg_mode(1) AND
    	NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)
    	OR (data(1).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2));

    FDCPE_cfg_mode2: FDCPE port map (cfg_mode(2),cfg_mode_D(2),NOT phi2short,'0','0');
    cfg_mode_D(2) <= ((cfg_mode(2) AND
    	NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)
    	OR (data(2).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2));

    FDCPE_cfg_mode3: FDCPE port map (cfg_mode(3),cfg_mode_D(3),NOT phi2short,'0','0');
    cfg_mode_D(3) <= ((cfg_mode(3) AND
    	NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)
    	OR (data(3).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2));

    FDCPE_cfg_mode4: FDCPE port map (cfg_mode(4),cfg_mode_D(4),NOT phi2short,'0','0');
    cfg_mode_D(4) <= ((cfg_mode(4) AND
    	NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)
    	OR (data(4).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2));

    FDCPE_cfg_mode5: FDCPE port map (cfg_mode(5),cfg_mode_D(5),NOT phi2short,'0','0');
    cfg_mode_D(5) <= ((cfg_mode(5) AND
    	NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2)
    	OR (data(5).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2));

    FDCPE_cfg_source_ram: FDCPE port map (cfg_source_ram,cfg_source_ram_D,NOT phi2short,'0','0');
    cfg_source_ram_D <= ((cfg_source_ram AND
    	NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)
    	OR (data(1).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2));

    FDCPE_cfg_source_ram2: FDCPE port map (cfg_source_ram2,cfg_source_ram2_D,NOT phi2short,'0','0');
    cfg_source_ram2_D <= ((cfg_source_ram2 AND
    	NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)
    	OR (data(3).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2));

    FDCPE_cfg_write_enable: FDCPE port map (cfg_write_enable,cfg_write_enable_D,NOT phi2short,'0','0');
    cfg_write_enable_D <= ((cfg_write_enable AND
    	NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)
    	OR (data(0).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2));

    FDCPE_cfg_write_enable2: FDCPE port map (cfg_write_enable2,cfg_write_enable2_D,NOT phi2short,'0','0');
    cfg_write_enable2_D <= ((cfg_write_enable2 AND
    	NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2)
    	OR (data(2).PIN AND reset_n_sync AND
    	use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2));

    data_I(0) <= ((rw AND NOT adr(3) AND adr(2) AND adr(0) AND cfg_enable2 AND
    	NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_mode(0) AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(13) AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT cctl AND NOT adr(1) AND
    	cfg_bank(21) AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
    	cfg_bank(13) AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND adr(2) AND adr(0) AND
    	cfg_write_enable AND NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (ram_rom_data(0).PIN AND NOT data_or0000/data_or0000_D2)
    	OR (rw AND NOT cctl AND cfg_bank(14) AND
    	data_or0000/data_or0000_D2 AND N247/N247_D2)
    	OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_bank2(21) AND
    	NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND adr(1) AND
    	cfg_enable AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	data_or0000/data_or0000_D2));
    data(0) <= data_I(0) when data_OE(0) = '1' else 'Z';
    data_OE(0) <= data_7_IOBUFE/data_7_IOBUFE_TRST;

    data_I(1) <= ((rw AND NOT adr(3) AND adr(2) AND adr(0) AND cfg_source_ram AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_mode(1) AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_bank2(22) AND
    	NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank(22) AND
    	NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (ram_rom_data(1).PIN AND NOT data_or0000/data_or0000_D2)
    	OR (rw AND NOT cctl AND cfg_bank(15) AND
    	data_or0000/data_or0000_D2 AND N247/N247_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(14) AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
    	cfg_bank(14) AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	data_or0000/data_or0000_D2));
    data(1) <= data_I(1) when data_OE(1) = '1' else 'Z';
    data_OE(1) <= data_7_IOBUFE/data_7_IOBUFE_TRST;

    data_I(2) <= ((rw AND NOT adr(3) AND adr(2) AND adr(0) AND
    	cfg_write_enable2 AND NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_mode(2) AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_bank2(23) AND
    	NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank(23) AND
    	NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (ram_rom_data(2).PIN AND NOT data_or0000/data_or0000_D2)
    	OR (rw AND NOT cctl AND cfg_bank(16) AND
    	data_or0000/data_or0000_D2 AND N247/N247_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(15) AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
    	cfg_bank(15) AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	data_or0000/data_or0000_D2));
    data(2) <= data_I(2) when data_OE(2) = '1' else 'Z';
    data_OE(2) <= data_7_IOBUFE/data_7_IOBUFE_TRST;

    data_I(3) <= ((rw AND NOT adr(3) AND adr(2) AND adr(0) AND
    	cfg_source_ram2 AND NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_mode(3) AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_bank2(24) AND
    	NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank(24) AND
    	NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (ram_rom_data(3).PIN AND NOT data_or0000/data_or0000_D2)
    	OR (rw AND NOT cctl AND cfg_bank(17) AND
    	data_or0000/data_or0000_D2 AND N247/N247_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(16) AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
    	cfg_bank(16) AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	data_or0000/data_or0000_D2));
    data(3) <= data_I(3) when data_OE(3) = '1' else 'Z';
    data_OE(3) <= data_7_IOBUFE/data_7_IOBUFE_TRST;

    data_I(4) <= ((rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_mode(4) AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_bank2(25) AND
    	NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank(25) AND
    	NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (ram_rom_data(4).PIN AND NOT data_or0000/data_or0000_D2)
    	OR (rw AND NOT cctl AND cfg_bank(18) AND
    	data_or0000/data_or0000_D2 AND N247/N247_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(17) AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
    	cfg_bank(17) AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	data_or0000/data_or0000_D2));
    data(4) <= data_I(4) when data_OE(4) = '1' else 'Z';
    data_OE(4) <= data_7_IOBUFE/data_7_IOBUFE_TRST;

    data_I(5) <= ((rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_mode(5) AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND cfg_bank2(26) AND
    	NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(18) AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank(26) AND
    	NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (ram_rom_data(5).PIN AND NOT data_or0000/data_or0000_D2)
    	OR (rw AND cfg_mode(0) AND NOT cctl AND cfg_bank(19) AND
    	data_or0000/data_or0000_D2 AND N247/N247_D2)
    	OR (rw AND NOT cfg_mode(0) AND sic_8xxx_enable AND NOT cctl AND
    	data_or0000/data_or0000_D2 AND N247/N247_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
    	cfg_bank(18) AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	data_or0000/data_or0000_D2));
    data(5) <= data_I(5) when data_OE(5) = '1' else 'Z';
    data_OE(5) <= data_7_IOBUFE/data_7_IOBUFE_TRST;

    data_I(6) <= ((rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(19) AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (ram_rom_data(6).PIN AND NOT data_or0000/data_or0000_D2)
    	OR (rw AND cfg_mode(0) AND NOT cctl AND cfg_bank(20) AND
    	data_or0000/data_or0000_D2 AND N247/N247_D2)
    	OR (rw AND NOT cfg_mode(0) AND NOT sic_axxx_enable AND NOT cctl AND
    	data_or0000/data_or0000_D2 AND N247/N247_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
    	cfg_bank(19) AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	data_or0000/data_or0000_D2));
    data(6) <= data_I(6) when data_OE(6) = '1' else 'Z';
    data_OE(6) <= data_7_IOBUFE/data_7_IOBUFE_TRST;

    data_I(7) <= ((rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND cfg_bank2(20) AND
    	NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND data_or0000/data_or0000_D2)
    	OR (rw AND NOT adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
    	cfg_bank(20) AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	data_or0000/data_or0000_D2)
    	OR (ram_rom_data(7).PIN AND NOT data_or0000/data_or0000_D2)
    	OR (rw AND cfg_mode(0) AND NOT cctl AND cfg_bank(21) AND
    	data_or0000/data_or0000_D2 AND N247/N247_D2)
    	OR (rw AND adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
    	eeprom_so AND cctl_access_and0000/cctl_access_and0000_D2 AND
    	data_or0000/data_or0000_D2));
    data(7) <= data_I(7) when data_OE(7) = '1' else 'Z';
    data_OE(7) <= data_7_IOBUFE/data_7_IOBUFE_TRST;

    data_7_IOBUFE/data_7_IOBUFE_TRST <= ((rw AND phi2 AND data_or0000/data_or0000_D2)
    	OR (rw AND phi2 AND
    	do_access_mux0002/do_access_mux0002_D2));

    data_or0000/data_or0000_D2 <= ((rw AND NOT adr(3) AND NOT cctl AND
    	cctl_access_and0000/cctl_access_and0000_D2)
    	OR (rw AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2)
    	OR (rw AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(3) AND
    	NOT cfg_mode(4) AND NOT cfg_mode(1) AND NOT cctl AND NOT adr(6) AND NOT adr(7) AND NOT adr(5)));

    do_access_mux0002/do_access_mux0002_D2 <= ((NOT s4 AND rd4 AND $OpTx$INV$433)
    	OR (NOT s5 AND rd5 AND $OpTx$INV$433 AND
    	use_cart_logic/N23/use_cart_logic/N23_D2)
    	OR (NOT s5 AND rd5 AND $OpTx$INV$433 AND
    	use_cart_logic/N11/use_cart_logic/N11_D2));

    FDCPE_eeprom_cs: FDCPE port map (eeprom_cs,eeprom_cs_D,NOT phi2short,'0','0');
    eeprom_cs_D <= ((NOT eeprom_cs AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (NOT data(1).PIN AND reset_n_sync AND
    	use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2));

    FDCPE_eeprom_sck: FDCPE port map (eeprom_sck,eeprom_sck_D,NOT phi2short,'0','0');
    eeprom_sck_D <= ((eeprom_sck AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (data(0).PIN AND reset_n_sync AND
    	use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2));

    FDCPE_eeprom_si: FDCPE port map (eeprom_si,eeprom_si_D,NOT phi2short,'0','0');
    eeprom_si_D <= ((NOT eeprom_si AND
    	NOT use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2)
    	OR (NOT data(7).PIN AND reset_n_sync AND
    	use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2));

    FDCPE_mod_en: FDCPE port map (mod_en,mod_en_D,NOT phi2short,'0','0');
    mod_en_D <= ((mod_en AND reset_n_sync)
    	OR (NOT rw AND adr(2) AND adr(0) AND NOT cctl AND adr(1) AND
    	NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 AND cctl_access_and0000/cctl_access_and0000_D2));

    FDCPE_oss_bank1: FDCPE port map (oss_bank(1),oss_bank_D(1),NOT phi2short,'0','0');
    oss_bank_D(1) <= ((oss_bank(1) AND
    	NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2)
    	OR (adr(0) AND reset_n_sync AND
    	use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2));

    ram_ce <= NOT (((cfg_source_ram AND
    	do_access_mux0002/do_access_mux0002_D2 AND use_cart_logic/N23/use_cart_logic/N23_D2)
    	OR (cfg_source_ram2 AND
    	do_access_mux0002/do_access_mux0002_D2 AND use_cart_logic/N16/use_cart_logic/N16_D2)));

    ram_rom_adr(0) <= adr(0);

    ram_rom_adr(1) <= adr(1);

    ram_rom_adr(2) <= adr(2);

    ram_rom_adr(3) <= adr(3);

    ram_rom_adr(4) <= adr(4);

    ram_rom_adr(5) <= adr(5);

    ram_rom_adr(6) <= adr(6);

    ram_rom_adr(7) <= adr(7);

    ram_rom_adr(8) <= adr(8);

    ram_rom_adr(9) <= adr(9);

    ram_rom_adr(10) <= adr(10);

    ram_rom_adr(11) <= adr(11);

    ram_rom_adr(12) <= ((cfg_mode(4) AND adr(12))
    	OR (adr(12) AND NOT $OpTx$FX_DC$483)
    	OR (NOT cfg_mode(4) AND use_cart_logic/oss_bank(0) AND
    	NOT adr(12) AND $OpTx$FX_DC$483));

    ram_rom_adr(13) <= ((cfg_mode(4) AND NOT s5 AND
    	use_cart_logic/N23/use_cart_logic/N23_D2)
    	OR (s4 AND cfg_mode(5) AND NOT cfg_mode(4) AND
    	use_cart_logic/N11/use_cart_logic/N11_D2)
    	OR (oss_bank(1) AND NOT adr(12) AND
    	use_cart_logic/N23/use_cart_logic/N23_D2 AND $OpTx$FX_DC$483)
    	OR (s4 AND cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(4) AND
    	use_cart_logic/N23/use_cart_logic/N23_D2)
    	OR (cfg_mode(4) AND cfg_bank(13))
    	OR (cfg_bank2(13) AND
    	use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (s4 AND cfg_bank(13) AND
    	NOT use_cart_logic/N11/use_cart_logic/N11_D2)
    	OR (NOT cfg_mode(5) AND cfg_bank(13) AND NOT $OpTx$FX_DC$483)
    	OR (cfg_mode(1) AND cfg_bank(13) AND
    	NOT use_cart_logic/N23/use_cart_logic/N23_D2));

    ram_rom_adr(14) <= ((cfg_mode(4) AND NOT s5 AND
    	use_cart_logic/N23/use_cart_logic/N23_D2)
    	OR (cfg_bank2(14) AND
    	use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_bank(14) AND
    	NOT use_cart_logic/N16/use_cart_logic/N16_D2));

    ram_rom_adr(15) <= ((cfg_bank2(15) AND
    	use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_bank(15) AND
    	NOT use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_mode(4) AND NOT s5 AND
    	use_cart_logic/N23/use_cart_logic/N23_D2 AND NOT $OpTx$FX_DC$451));

    ram_rom_adr(16) <= ((cfg_bank2(16) AND
    	use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_bank(16) AND
    	NOT use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_mode(2) AND cfg_mode(4) AND NOT s5 AND
    	use_cart_logic/N23/use_cart_logic/N23_D2)
    	OR (cfg_mode(4) AND cfg_mode(1) AND NOT s5 AND
    	use_cart_logic/N23/use_cart_logic/N23_D2));

    ram_rom_adr(17) <= ((cfg_bank2(17) AND
    	use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_bank(17) AND
    	NOT use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_mode(2) AND cfg_mode(4) AND NOT s5 AND
    	use_cart_logic/N23/use_cart_logic/N23_D2)
    	OR (cfg_mode(0) AND cfg_mode(4) AND cfg_mode(1) AND NOT s5 AND
    	use_cart_logic/N23/use_cart_logic/N23_D2));

    ram_rom_adr(18) <= ((cfg_bank2(18) AND
    	use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_bank(18) AND
    	NOT use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_mode(2) AND cfg_mode(5) AND cfg_mode(4) AND
    	NOT cfg_mode(1) AND NOT s5));

    ram_rom_adr(19) <= ((cfg_bank2(19) AND
    	use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_bank(19) AND
    	NOT use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_mode(0) AND cfg_mode(2) AND cfg_mode(5) AND
    	cfg_mode(4) AND NOT cfg_mode(1) AND NOT s5));

    ram_rom_adr(20) <= ((cfg_bank2(20) AND
    	use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_bank(20) AND
    	NOT use_cart_logic/N16/use_cart_logic/N16_D2));

    ram_rom_adr(21) <= ((cfg_bank2(21) AND
    	use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_bank(21) AND
    	NOT use_cart_logic/N16/use_cart_logic/N16_D2));

    ram_rom_adr(22) <= ((cfg_bank2(22) AND
    	use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_bank(22) AND
    	NOT use_cart_logic/N16/use_cart_logic/N16_D2));

    ram_rom_adr(23) <= ((cfg_bank2(23) AND
    	use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_bank(23) AND
    	NOT use_cart_logic/N16/use_cart_logic/N16_D2));

    ram_rom_adr(24) <= ((cfg_bank(24) AND
    	NOT use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_bank2(24) AND
    	use_cart_logic/N16/use_cart_logic/N16_D2));

    ram_rom_adr(25) <= ((cfg_bank2(25) AND
    	use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_bank(25) AND
    	NOT use_cart_logic/N16/use_cart_logic/N16_D2));

    ram_rom_adr(26) <= ((cfg_bank2(26) AND
    	use_cart_logic/N16/use_cart_logic/N16_D2)
    	OR (cfg_bank(26) AND
    	NOT use_cart_logic/N16/use_cart_logic/N16_D2));

    ram_rom_data_I(0) <= data(0).PIN;
    ram_rom_data(0) <= ram_rom_data_I(0) when ram_rom_data_OE(0) = '1' else 'Z';
    ram_rom_data_OE(0) <= NOT rw;

    ram_rom_data_I(1) <= data(1).PIN;
    ram_rom_data(1) <= ram_rom_data_I(1) when ram_rom_data_OE(1) = '1' else 'Z';
    ram_rom_data_OE(1) <= NOT rw;

    ram_rom_data_I(2) <= data(2).PIN;
    ram_rom_data(2) <= ram_rom_data_I(2) when ram_rom_data_OE(2) = '1' else 'Z';
    ram_rom_data_OE(2) <= NOT rw;

    ram_rom_data_I(3) <= data(3).PIN;
    ram_rom_data(3) <= ram_rom_data_I(3) when ram_rom_data_OE(3) = '1' else 'Z';
    ram_rom_data_OE(3) <= NOT rw;

    ram_rom_data_I(4) <= data(4).PIN;
    ram_rom_data(4) <= ram_rom_data_I(4) when ram_rom_data_OE(4) = '1' else 'Z';
    ram_rom_data_OE(4) <= NOT rw;

    ram_rom_data_I(5) <= data(5).PIN;
    ram_rom_data(5) <= ram_rom_data_I(5) when ram_rom_data_OE(5) = '1' else 'Z';
    ram_rom_data_OE(5) <= NOT rw;

    ram_rom_data_I(6) <= data(6).PIN;
    ram_rom_data(6) <= ram_rom_data_I(6) when ram_rom_data_OE(6) = '1' else 'Z';
    ram_rom_data_OE(6) <= NOT rw;

    ram_rom_data_I(7) <= data(7).PIN;
    ram_rom_data(7) <= ram_rom_data_I(7) when ram_rom_data_OE(7) = '1' else 'Z';
    ram_rom_data_OE(7) <= NOT rw;

    ram_rom_oe <= NOT ((rw AND phi2));

    ram_rom_we <= NOT ((NOT rw AND phi2short));

    rd4 <= ((cfg_mode(0) AND cfg_mode(5) AND NOT cfg_mode(1) AND
    	cfg_enable)
    	OR (NOT cfg_mode(2) AND cfg_mode(5) AND cfg_mode(1) AND
    	cfg_enable)
    	OR (cfg_mode(2) AND cfg_mode(5) AND NOT cfg_mode(1) AND
    	sic_8xxx_enable AND cfg_enable)
    	OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(5) AND
    	NOT cfg_mode(3) AND NOT cfg_mode(4) AND NOT cfg_mode(1) AND cfg_enable2)
    	OR (cfg_mode(5) AND cfg_mode(3) AND NOT cfg_mode(4) AND
    	cfg_enable)
    	OR (cfg_mode(5) AND cfg_mode(4) AND NOT cfg_mode(1) AND
    	cfg_enable));

    rd5 <= ((NOT cfg_mode(4) AND cfg_enable AND
    	use_cart_logic/N11/use_cart_logic/N11_D2)
    	OR (cfg_mode(0) AND cfg_mode(5) AND NOT cfg_mode(1) AND
    	cfg_enable)
    	OR (cfg_mode(5) AND cfg_mode(4) AND NOT cfg_mode(1) AND
    	cfg_enable)
    	OR (cfg_mode(5) AND NOT cfg_mode(1) AND sic_axxx_enable AND
    	cfg_enable)
    	OR (NOT cfg_mode(2) AND cfg_mode(5) AND cfg_enable));

    FDCPE_reset_n_sync: FDCPE port map (reset_n_sync,reset_n_sync1,NOT phi2short,'0','0');

    FDCPE_reset_n_sync1: FDCPE port map (reset_n_sync1,reset_n,NOT phi2short,'0','0');

    rom_ce <= ((NOT do_access_mux0002/do_access_mux0002_D2)
    	OR (cfg_source_ram AND
    	use_cart_logic/N23/use_cart_logic/N23_D2)
    	OR (cfg_source_ram2 AND
    	use_cart_logic/N16/use_cart_logic/N16_D2));

    FDCPE_rom_reset: FDCPE port map (rom_reset,'1',NOT phi2short,'0','0',reset_n_sync);

    FDCPE_sic_8xxx_enable: FDCPE port map (sic_8xxx_enable,sic_8xxx_enable_D,NOT phi2short,'0','0');
    sic_8xxx_enable_D <= ((sic_8xxx_enable AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (data(5).PIN AND reset_n_sync AND
    	use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2));

    FDCPE_sic_axxx_enable: FDCPE port map (sic_axxx_enable,sic_axxx_enable_D,NOT phi2short,'0','0');
    sic_axxx_enable_D <= ((NOT sic_axxx_enable AND
    	NOT use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2)
    	OR (data(6).PIN AND reset_n_sync AND
    	use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2));

    use_cart_logic/N11/use_cart_logic/N11_D2 <= ((NOT cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(5) AND
    	NOT cfg_mode(1) AND oss_bank(1))
    	OR (NOT cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(5) AND
    	NOT cfg_mode(1) AND use_cart_logic/oss_bank(0))
    	OR (cfg_mode(5) AND cfg_mode(3))
    	OR (cfg_mode(3) AND NOT cfg_mode(1))
    	OR (cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(3))
    	OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(1)));

    use_cart_logic/N16/use_cart_logic/N16_D2 <= (NOT s4 AND cfg_mode(5) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND
    	$OpTx$FX_DC$451);

    use_cart_logic/N23/use_cart_logic/N23_D2 <= ((cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(4) AND
    	NOT cfg_mode(1))
    	OR (NOT cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(4) AND
    	NOT cfg_mode(1))
    	OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(4) AND
    	cfg_mode(1))
    	OR (cfg_mode(5) AND cfg_mode(3) AND NOT cfg_mode(4))
    	OR (cfg_mode(5) AND
    	NOT use_cart_logic/N16/use_cart_logic/N16_D2 AND NOT $OpTx$FX_DC$444)
    	OR (cfg_mode(3) AND NOT cfg_mode(4) AND NOT cfg_mode(1))
    	OR (NOT cfg_mode(2) AND NOT cfg_mode(3) AND NOT cfg_mode(4) AND
    	cfg_mode(1)));

    use_cart_logic/N252/use_cart_logic/N252_D2 <= ((cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND
    	adr(6) AND adr(7) AND NOT adr(5) AND adr(4))
    	OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND cfg_mode(1) AND
    	adr(6) AND NOT adr(7) AND adr(5) AND adr(4))
    	OR (NOT cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(1) AND
    	adr(6) AND adr(7) AND adr(5) AND NOT adr(4)));

    use_cart_logic/N69/use_cart_logic/N69_D2 <= ((cfg_mode(0) AND NOT cfg_mode(2) AND NOT cfg_mode(3) AND
    	cfg_mode(1) AND NOT adr(7))
    	OR (NOT cfg_mode(2) AND NOT cfg_mode(3) AND cfg_mode(1) AND
    	NOT adr(7) AND $OpTx$FX_DC$457)
    	OR (cfg_mode(0) AND cfg_mode(2) AND cfg_mode(3) AND
    	NOT cfg_mode(1) AND NOT adr(7) AND $OpTx$FX_DC$457));

    use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2 <= ((NOT reset_n_sync)
    	OR (NOT rw AND NOT adr(3) AND adr(0) AND NOT cctl AND adr(1) AND
    	NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 AND cctl_access_and0000/cctl_access_and0000_D2));

    use_cart_logic/cfg_bank2_21__or0000/use_cart_logic/cfg_bank2_21__or0000_D2 <= ((NOT reset_n_sync)
    	OR (NOT rw AND NOT adr(3) AND adr(2) AND NOT adr(0) AND NOT cctl AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2));

    use_cart_logic/cfg_bank_22__or0000/use_cart_logic/cfg_bank_22__or0000_D2 <= ((NOT reset_n_sync)
    	OR (NOT rw AND NOT adr(3) AND NOT adr(2) AND adr(0) AND NOT cctl AND
    	cctl_access_and0000/cctl_access_and0000_D2 AND
    	NOT use_cart_logic/cfg_bank2_13__or0000/use_cart_logic/cfg_bank2_13__or0000_D2));

    use_cart_logic/cfg_mode_0__or0001/use_cart_logic/cfg_mode_0__or0001_D2 <= ((NOT reset_n_sync)
    	OR (NOT rw AND NOT adr(3) AND adr(2) AND NOT cctl AND adr(1) AND
    	NOT use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 AND cctl_access_and0000/cctl_access_and0000_D2));

    use_cart_logic/cfg_source_ram2__or0000/use_cart_logic/cfg_source_ram2__or0000_D2 <= ((NOT reset_n_sync)
    	OR (NOT rw AND NOT adr(3) AND adr(2) AND adr(0) AND NOT cctl AND adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2));

    FDCPE_use_cart_logic/oss_bank0: FDCPE port map (use_cart_logic/oss_bank(0),use_cart_logic/oss_bank_D(0),NOT phi2short,'0','0');
    use_cart_logic/oss_bank_D(0) <= ((use_cart_logic/oss_bank(0) AND
    	NOT use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2)
    	OR (NOT adr(3) AND reset_n_sync AND
    	use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2));

    use_cart_logic/oss_bank_0__or0000/use_cart_logic/oss_bank_0__or0000_D2 <= ((NOT reset_n_sync)
    	OR (NOT cfg_mode(0) AND cfg_mode(2) AND NOT cfg_mode(5) AND
    	NOT cfg_mode(3) AND NOT cfg_mode(4) AND NOT cfg_mode(1) AND NOT cctl AND
    	NOT cctl_access_and0000/cctl_access_and0000_D2));

    use_cart_logic/sic_8xxx_enable__or0000/use_cart_logic/sic_8xxx_enable__or0000_D2 <= ((NOT reset_n_sync)
    	OR (NOT rw AND NOT cfg_mode(0) AND cfg_mode(2) AND cfg_mode(5) AND
    	NOT cfg_mode(3) AND NOT cfg_mode(4) AND NOT cfg_mode(1) AND NOT cctl AND NOT adr(6) AND
    	NOT adr(7) AND NOT adr(5)));

    use_cart_spi/cs__or0001/use_cart_spi/cs__or0001_D2 <= ((NOT reset_n_sync)
    	OR (NOT rw AND adr(3) AND NOT adr(2) AND NOT adr(0) AND NOT cctl AND NOT adr(1) AND
    	cctl_access_and0000/cctl_access_and0000_D2));

    Register Legend:
     FDCPE (Q,D,C,CLR,PRE,CE);
     FTCPE (Q,D,C,CLR,PRE,CE);
     LDCP  (Q,D,G,CLR,PRE);

    ******************************  Device Pin Out *****************************

    Device : XC95144XL-10-TQ100

       --------------------------------------------------
      /100 98  96  94  92  90  88  86  84  82  80  78  76  \
     |   99  97  95  93  91  89  87  85  83  81  79  77    |
     | 1                                               75  |
     | 2                                               74  |
     | 3                                               73  |
     | 4                                               72  |
     | 5                                               71  |
     | 6                                               70  |
     | 7                                               69  |
     | 8                                               68  |
     | 9                                               67  |
     | 10                                              66  |
     | 11                                              65  |
     | 12                                              64  |
     | 13              XC95144XL-10-TQ100              63  |
     | 14                                              62  |
     | 15                                              61  |
     | 16                                              60  |
     | 17                                              59  |
     | 18                                              58  |
     | 19                                              57  |
     | 20                                              56  |
     | 21                                              55  |
     | 22                                              54  |
     | 23                                              53  |
     | 24                                              52  |
     | 25                                              51  |
     |   27  29  31  33  35  37  39  41  43  45  47  49    |
      \26  28  30  32  34  36  38  40  42  44  46  48  50  /
       --------------------------------------------------

    Pin Signal                         Pin Signal
    No. Name                           No. Name
      1 data<4>                          51 VCC
      2 PGND                             52 ram_rom_adr<2>
      3 s4                               53 ram_rom_adr<3>
      4 s5                               54 ram_rom_adr<4>
      5 VCC                              55 ram_rom_adr<5>
      6 data<5>                          56 ram_rom_adr<6>
      7 PGND                             57 VCC
      8 data<2>                          58 ram_rom_adr<7>
      9 data<1>                          59 ram_rom_adr<8>
     10 data<3>                          60 ram_rom_adr<18>
     11 data<0>                          61 ram_rom_adr<19>
     12 data<7>                          62 GND
     13 data<6>                          63 ram_rom_adr<22>
     14 adr<11>                          64 ram_rom_adr<21>
     15 adr<10>                          65 ram_rom_adr<20>
     16 eeprom_cs                        66 ram_rom_adr<9>
     17 eeprom_so                        67 ram_rom_adr<10>
     18 eeprom_sck                       68 ram_rom_adr<11>
     19 PGND                             69 GND
     20 eeprom_si                        70 ram_rom_adr<12>
     21 GND                              71 ram_rom_adr<13>
     22 phi2                             72 ram_rom_adr<14>
     23 phi2short                        73 mod_en
     24 ram_rom_adr<26>                  74 ram_rom_adr<15>
     25 ram_rom_adr<0>                   75 GND
     26 VCC                              76 ram_rom_adr<16>
     27 cctl                             77 ram_rom_adr<23>
     28 ram_rom_adr<17>                  78 ram_rom_adr<24>
     29 ram_rom_adr<25>                  79 rd5
     30 rom_reset                        80 PGND
     31 GND                              81 rd4
     32 ram_rom_data<7>                  82 reset_n
     33 ram_rom_data<6>                  83 TDO
     34 PGND                             84 GND
     35 ram_rom_data<5>                  85 ram_ce
     36 ram_rom_data<4>                  86 adr<3>
     37 ram_rom_data<3>                  87 adr<4>
     38 VCC                              88 VCC
     39 ram_rom_data<2>                  89 adr<2>
     40 ram_rom_data<1>                  90 adr<5>
     41 ram_rom_data<0>                  91 adr<1>
     42 ram_rom_oe                       92 adr<6>
     43 ram_rom_adr<1>                   93 adr<0>
     44 GND                              94 adr<7>
     45 TDI                              95 adr<8>
     46 PGND                             96 adr<9>
     47 TMS                              97 adr<12>
     48 TCK                              98 VCC
     49 rom_ce                           99 rw
     50 ram_rom_we                      100 GND

    Legend :  NC  = Not Connected, unbonded pin
             PGND = Unused I/O configured as additional Ground pin
             TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
             KPR  = Unused I/O with weak keeper (leave unconnected)
             VCC  = Dedicated Power Pin
             GND  = Dedicated Ground Pin
             TDI  = Test Data In, JTAG pin
             TDO  = Test Data Out, JTAG pin
             TCK  = Test Clock, JTAG pin
             TMS  = Test Mode Select, JTAG pin
      PROHIBITED  = User reserved pin
    ****************************  Compiler Options  ****************************

    Following is a list of all global compiler options used by the fitter run.

    Device(s) Specified                         : xc95144xl-10-TQ100
    Optimization Method                         : DENSITY
    Multi-Level Logic Optimization              : ON
    Ignore Timing Specifications                : OFF
    Default Register Power Up Value             : LOW
    Keep User Location Constraints              : ON
    What-You-See-Is-What-You-Get                : OFF
    Exhaustive Fitting                          : OFF
    Keep Unused Inputs                          : OFF
    Slew Rate                                   : SLOW
    Power Mode                                  : LOW
    Ground on Unused IOs                        : ON
    Set I/O Pin Termination                     : KEEPER
    Global Clock Optimization                   : ON
    Global Set/Reset Optimization               : ON
    Global Ouput Enable Optimization            : ON
    Input Limit                                 : 54
    Pterm Limit                                 : 90